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54ACT16652 PDF预览

54ACT16652

更新时间: 2024-02-25 14:19:05
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德州仪器 - TI 输出元件
页数 文件大小 规格书
11页 197K
描述
16-BIT TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

54ACT16652 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP, FL56,.4,25针数:56
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:N其他特性:SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:ACTJESD-30 代码:R-GDFP-F56
长度:18.288 mm负载电容(CL):50 pF
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER最大I(ol):0.05 A
位数:8功能数量:2
端口数量:2端子数量:56
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL56,.4,25封装形状:RECTANGULAR
封装形式:FLATPACK电源:5 V
Prop。Delay @ Nom-Sup:10.5 ns传播延迟(tpd):12.3 ns
认证状态:Not Qualified座面最大高度:3.05 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:0.635 mm端子位置:DUAL
翻译:N/A触发器类型:POSITIVE EDGE
宽度:9.652 mmBase Number Matches:1

54ACT16652 数据手册

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54ACT16652, 74ACT16652  
16-BIT TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCAS128C – MARCH 1990 – REVISED APRIL 1996  
54ACT16652 . . . WD PACAGE  
74ACT16652 . . . DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
Inputs Are TTL-Voltage Compatible  
1OEAB  
1CLKAB  
1SAB  
GND  
1OEBA  
1CLKBA  
1SBA  
GND  
1B1  
1B2  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
Independent Registers and Enables for A  
and B Buses  
2
3
Multiplexed Real-Time and Stored Data  
4
Flow-Through Architecture Optimizes  
PCB Layout  
1A1  
1A2  
5
6
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
V
V
7
CC  
CC  
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
8
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
9
10  
11  
12  
13  
14  
15  
16  
17  
500-mA Typical Latch-Up Immunity at  
125°C  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) Packages Using  
25-mil Center-to-Center Pin Spacings and  
380-mil Fine-Pitch Ceramic Flat (WD)  
Packages Using 25-mil Center-to-Center  
Spacings  
GND 18  
2A4 19  
2A5 20  
2A6 21  
39 GND  
38 2B4  
37 2B5  
36 2B6  
description  
The ’ACT16652 are 16-bit bus transceivers  
consisting of D-type flip-flops and control circuitry  
arranged for multiplexed transmission of data  
directly from the data bus or from the internal  
storage registers. The devices can be used as two  
8-bit transceivers or one 16-bit transceiver.  
V
22  
35  
V
CC  
CC  
2A7 23  
34 2B7  
2A8 24  
33 2B8  
GND 25  
32 GND  
31 2SBA  
30 2CLKBA  
29 2OEBA  
2SAB 26  
2CLKAB 27  
2OEAB 28  
Complementary output-enable (OEAB and  
OEBA) inputs are provided to control the  
transceiver functions. Select-control (SAB and  
SBA) inputs are provided to select whether  
real-time or stored data is transferred. A low input  
level selects real-time data, and a high input level  
selects stored data. The circuitry used for select  
control eliminates the typical decoding glitch that  
occurs in a multiplexer during the transition  
between stored and real-time data. Figure 1  
illustrates the four fundamental bus-management  
functions that can be performed with the  
’ACT16652.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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