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54ACT16620 PDF预览

54ACT16620

更新时间： 2024-01-06 20:35:11
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
6页 125K
描述
16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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54ACT16620 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DFP包装说明：FINE PITCH, CERAMIC, FP-48
针数：48Reach Compliance Code：not_compliant
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.92Is Samacsys：N
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：ACT
JESD-30 代码：R-GDFP-F48长度：15.748 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.024 A位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装等效代码：FL48,.4,25
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：0.08 mAProp。Delay @ Nom-Sup：10.5 ns
传播延迟（tpd）：10.5 ns认证状态：Not Qualified
座面最大高度：3.05 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：FLAT端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：9.652 mm
Base Number Matches：1

54ACT16620 数据手册

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SCAS184A − JUNE 1990 − REVISED APRIL 1996  
54ACT16620 . . . WD PACKAGE  
74ACT16620 . . . DL PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
D
Members of the Texas Instruments  
Widebus Family  
Inputs Are TTL-Voltage Compatible  
Inverting Logic  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OEAB  
1B1  
1OEBA  
1A1  
Flow-Through Architecture Optimizes  
PCB Layout  
2
3
1B2  
1A2  
4
GND  
1B3  
GND  
1A3  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
5
6
1B4  
1A4  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
500-mA Typical Latch-Up Immunity at  
7
V
V
CC  
CC  
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
9
125°C  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) Packages Using  
25-mil Center-to-Center Pin Spacings and  
380-mil Fine-Pitch Ceramic Flat (WD)  
Packages Using 25-mil Center-to-Center  
Pin Spacings  
description  
V
V
CC  
CC  
2B5  
2B6  
GND  
2B7  
2B8  
2A5  
2A6  
GND  
2A7  
2A8  
The ’ACT16620 are inverting 16-bit transceivers  
designed for asynchronous communication  
between data buses. The control-function  
implementation allows for maximum flexibility in  
timing.  
2OEAB  
2OEBA  
These devices can be used as two 8-bit  
transceivers or one 16-bit transceiver. They allow  
data transmission from the A bus to the B bus or  
from the B bus to the A bus, depending on the logic  
level at the output-enable (OEAB or OEBA)  
inputs. The output-enable inputs can be used to  
disable the device so that the buses are effectively  
isolated.  
The dual-enable configuration gives the transceiver the capability to store data by simultaneously enabling  
OEAB and OEBA. Each output reinforces its input in this transceiver configuration. Thus, when both control  
inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, the bus lines  
remain at their last states.  
The 74ACT16620 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and  
functionality of standard small-outline packages in the same printed-circuit-board area.  
The 54ACT16620 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
74ACT16620 is characterized for operation from −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
123456

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