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54ACT11821 PDF预览

54ACT11821

更新时间: 2024-02-13 01:00:23
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
7页 124K
描述
10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

54ACT11821 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFN包装说明:QCCN, LCC28,.45SQ
针数:28Reach Compliance Code:not_compliant
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.92Is Samacsys:N
系列:ACTJESD-30 代码:S-CQCC-N28
长度:11.43 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
位数:10功能数量:1
端口数量:2端子数量:28
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC28,.45SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:12.9 ns
传播延迟(tpd):12.9 ns认证状态:Not Qualified
座面最大高度:2.03 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:11.43 mm
Base Number Matches:1

54ACT11821 数据手册

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SCAS156A − NOVEMBER 1990 − REVISED APRIL 1993  
54ACT11821 . . . JT PACKAGE  
74ACT11821 . . . DW PACKAGE  
Inputs Are TTL-Voltage Compatible  
Provides Extra Data Width Necessary for  
Wider Address/Data Paths or Buses With  
Parity  
(TOP VIEW)  
1Q  
2Q  
3Q  
OE  
1D  
2D  
1
28  
27  
26  
Flow-Through Architecture Optimizes  
2
PCB Layout  
3
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
4Q  
5Q  
4
25 3D  
CC  
5
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
4D  
5D  
V
6
GND  
GND  
GND  
GND  
6Q  
7Q  
8Q  
9Q  
10Q  
EPIC(Enhanced-Performance Implanted  
7
CMOS) 1-µm Process  
CC  
8
V
CC  
500-mA Typical Latch-Up Immunity at 125°C  
9
6D  
7D  
8D  
9D  
10D  
CLK  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Ceramic 300-mil  
DIPs  
10  
11  
12  
13  
14  
description  
These 10-bit flip-flops feature 3-state outputs  
designed specifically for driving highly-capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing wider buffer  
registers, I/O ports, bidirectional bus drivers with  
parity, and working registers.  
54ACT11821 . . . FK PACKAGE  
(TOP VIEW)  
4
3
2 1 28 27 26  
5
6
7
8
9
On the positive transition of the clock the Q outputs  
will follow the D inputs.  
2D  
1D  
OE  
1Q  
2Q  
3Q  
4Q  
25 8D  
24 9D  
10  
23  
22  
21  
20  
19  
A buffered output enable (OE) input can be used  
to place the ten outputs in either a normal logic  
state (high or low level) or a high-impedance state.  
In the high-impedance state the outputs neither  
load nor drive the bus lines significantly.  
CLK  
10Q  
9Q  
10  
8Q  
11  
12 13 14 15 16 17 18  
The high-impedance state and increased drive  
provide the capability to drive the bus lines in a  
bus-organized system without need for interface  
or pull-up components.  
The output enable (OE)does not affect the internal operation of the flip-flops. Old data can be retained or new  
data can be entered while the outputs are in the high-impedance state.  
The 54ACT11821 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
74ACT11821 is characterized for operation form 40°C to 85°C.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
ꢏ ꢑꢕ ꢒꢐꢐ ꢗ ꢄꢙ ꢒꢓꢘ ꢎꢐ ꢒ ꢑ ꢗꢄꢒ ꢜ ꢝꢞ ꢟꢠ ꢡꢢꢣ ꢤꢥ ꢦꢧꢝ ꢣꢢ ꢧꢝꢨ ꢟꢧꢠ ꢖꢓ ꢗ ꢜ ꢏ ꢃꢄ ꢎꢗ ꢑ  
ꢫꢨ ꢪ ꢨ ꢥ ꢦ ꢝ ꢦ ꢪ ꢠ ꢮ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  

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