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54ACT11109

更新时间: 2024-02-16 17:06:42
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
5页 73K
描述
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

54ACT11109 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.41
系列:ACTJESD-30 代码:R-GDIP-T16
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:J-KBAR FLIP-FLOP最大频率@ Nom-Sup:100000000 Hz
最大I(ol):0.024 A位数:2
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):9 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:100 MHzBase Number Matches:1

54ACT11109 数据手册

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54ACT11109, 74ACT11109  
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993  
54ACT11109 . . . J PACKAGE  
74ACT11109 . . . D OR N PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Flow-Through Architecture Optimizes  
PCB Layout  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
1CLK  
1K  
1J  
1PRE  
1Q  
1Q  
GND  
2Q  
2Q  
2PRE  
2CLK  
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
1CLR  
V
CC  
500-mA Typical Latch-Up Immunity  
at 125°C  
2CLR  
2J  
2K  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and  
Ceramic 300-mil DIPs  
54ACT11109 . . . FK PACKAGE  
(TOP VIEW)  
description  
These devices contain two independent J-K  
positive-edge-triggered flip-flops. A low level at  
the preset (1PRE or 2PRE) or clear (1CLR or  
2CLR) input sets or resets the outputs regardless  
of the levels of the other inputs. When PRE and  
CLR are inactive (high), data at the J and K inputs  
meeting the setup time requirements are  
transferred to the outputs on the positive-going  
edge of the clock pulse. Clock triggering occurs at  
a voltage level and is not directly related to the rise  
time of the clock pulse. Following the hold-time  
interval, data at the J and K inputs may be  
changed without affecting the levels at the  
outputs. These versatile flip-flops can perform as  
toggle flip-flops by grounding K and tying J high.  
They also can perform as D-type flip-flops if J and  
K are tied together.  
3
2
1
20 19  
18  
2J  
1K  
1CLK  
NC  
4
5
6
7
8
2K  
17  
16  
15  
14  
NC  
2CLK  
2PRE  
1PRE  
1Q  
9 10 11 12 13  
NC – No internal connection  
The 54ACT11109 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
74ACT11109 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
H
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
H
L
L
X
H
H
H
L
H
H
H
H
L
L
Toggle  
H
H
H
H
X
Q
Q
0
0
H
H
H
X
H
L
H
H
L
Q
0
Q
0
Thisconfigurationisnonstable;thatis, itwillnotpersistwhen  
either PRE or CLR returns to the inactive (high) level.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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