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1P1G125QDCKRQ1 PDF预览

1P1G125QDCKRQ1

更新时间: 2024-01-23 10:15:42
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路光电二极管输出元件驱动
页数 文件大小 规格书
8页 102K
描述
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

1P1G125QDCKRQ1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SC-70, 5 PIN针数:5
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.78Is Samacsys:N
控制类型:ENABLE LOW计数方向:UNIDIRECTIONAL
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G5
JESD-609代码:e4长度:2 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.032 A湿度敏感等级:1
位数:1功能数量:1
端口数量:2端子数量:5
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP5/6,.08封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):260电源:3.3 V
最大电源电流(ICC):0.01 mAProp。Delay @ Nom-Sup:5.1 ns
传播延迟(tpd):5.1 ns认证状态:Not Qualified
筛选级别:AEC-Q100座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:1.25 mm
Base Number Matches:1

1P1G125QDCKRQ1 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢇ ꢉꢊꢋ ꢌꢇ  
ꢀꢍ ꢁꢈ ꢄ ꢎ ꢏꢐꢀ ꢏꢐꢑ ꢑꢎ ꢒ ꢈ ꢓꢔꢎ  
ꢕ ꢍꢔ ꢖ ꢗ ꢋꢀꢔꢓꢔ ꢎ ꢘ ꢐꢔ ꢙꢐ ꢔ  
SGES002A − APRIL 2003 − REVISED MAY 2004  
D
Qualification in Accordance With  
AEC-Q100  
D
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
D
Qualified for Automotive Applications  
Latch-Up Performance Exceeds 100 mA  
Per JESD 78, Class II  
D
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
D
D
D
D
D
Supports 5-V V  
Operation  
CC  
DCK PACKAGE  
(TOP VIEW)  
Inputs Accept Voltages to 5.5 V  
Max t of 3.7 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
24-mA Output Drive at 3.3 V  
1
2
3
5
4
OE  
A
V
Y
CC  
CC  
GND  
Contact factory for details. Q100 qualification data available on  
request.  
description/ordering information  
This bus buffer gate is designed for 1.65-V to 5.5-V V  
operation.  
CC  
The SN74LVC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable  
(OE) input is high.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
§
−40°C to 125°C SOT (SC-70) − DCK  
Reel of 2875  
1P1G125QDCKRQ1  
CM_  
§
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
ꢔꢦ  
Copyright 2004, Texas Instruments Incorporated  
ꢢꢦ ꢣ ꢢ ꢛꢜ ꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢꢦ ꢟꢣ ꢫ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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