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1633966

更新时间: 2022-06-03 04:17:54
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德州仪器 - TI /
页数 文件大小 规格书
20页 756K
描述
2:4 Low Additive Jitter LVDS Buffer

1633966 数据手册

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CDCLVD1204  
www.ti.com  
SCAS898A MAY 2010REVISED JUNE 2010  
2:4 Low Additive Jitter LVDS Buffer  
Check for Samples: CDCLVD1204  
1
FEATURES  
DESCRIPTION  
2:4 Differential Buffer  
The CDCLVD1204 clock buffer distributes one of two  
selectable clock inputs, (IN0, IN1), to 4 pairs of  
differential LVDS clock outputs (OUT0, OUT3) with  
minimum skew for clock distribution. The  
CDCLVD1204 can accept two clock sources into an  
input multiplexer. The inputs can either be LVDS,  
LVPECL, or LVCMOS.  
Low Additive Jitter: <300 fs RMS in 10-kHz to  
20-MHz  
Low Output Skew of 20 ps (Max)  
Universal Inputs Accept LVDS, LVPECL, and  
LVCMOS  
Selectable Clock Inputs through Control Pin  
The CDCLVD1204 is specifically designed for driving  
50 Ω transmission lines. In case of driving the inputs  
in single ended mode, the appropriate bias voltage  
(VAC_REF) should be applied to the unused negative  
input pin.  
4 LVDS Outputs, ANSI EAI/TIA-644A Standard  
Compatible  
Clock Frequency up to 800 MHz  
2.375 V–2.625 V Device Power Supply  
The IN_SEL pin selects the input which is routed to  
the outputs. If this pin is left open it disables the  
outputs (static). The part supports a fail safe function.  
The device incorporates an input hysteresis which  
prevents random oscillation of the outputs in the  
absence of an input signal.  
LVDS Reference Voltage, VAC_REF, Available for  
Capacitive Coupled Inputs  
Industrial Temperature Range: –40°C to 85°C  
Packaged in 3 mm × 3 mm 16-Pin QFN (RGT)  
ESD Protection Exceeds 3 kV HBM, 1 kV CDM  
The device operates in 2.5V supply environment and  
is characterized from –40°C to 85°C (ambient  
temperature). The CDCLVD1204 is packaged in  
small 16-pin, 3-mm × 3-mm QFN package.  
APPLICATIONS  
Telecommunications/Networking  
Medical Imaging  
Test and Measurement Equipment  
Wireless Communications  
General Purpose Clocking  
ASIC  
PHY1  
PHY2  
156.25 MHz  
Oscillator  
(156.25  
MHz)  
CDCLVD1204  
LVDS Buffer  
IN_SEL  
FPGA  
Figure 1. Application Example  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010, Texas Instruments Incorporated  
 

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