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TFP201PZP PDF预览

TFP201PZP

更新时间: 2024-01-10 09:19:36
品牌 Logo 应用领域
德州仪器 - TI 接收机
页数 文件大小 规格书
18页 284K
描述
TI PANEL BUS DIGITAL RECEIVER

TFP201PZP 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:HTFQFP, TQFP100,.63SQ
针数:100Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.8商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PQFP-G100JESD-609代码:e4
长度:14 mm湿度敏感等级:3
功能数量:1端子数量:100
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:HTFQFP
封装等效代码:TQFP100,.63SQ封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Other Consumer ICs
最大压摆率:350 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

TFP201PZP 数据手册

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SLDS116A - MARCH 2000 – REVISED JUNE 2000  
D
D
D
D
Supports SXGA Resolution  
(Output Pixel Rates Up to 112 MHz)  
D
D
D
D
D
Reduced Power Consumption – 1.8 V Core  
Operation With 3.3 V I/Os and Supplies  
2
Digital Visual Interface (DVI) Specification  
Reduced Ground Bounce Using Time  
Staggered Pixel Outputs  
1
Compliant  
True-Color, 24 Bit/Pixel, 16.7M Colors at 1  
or 2-Pixels Per Clock  
Lowest Noise and Best Power Dissipation  
Using TI PowerPAD Packaging  
Laser Trimmed Internal Termination  
Resistors for Optimum Fixed Impedance  
Matching  
Advanced Technology Using TI 0.18-µm  
EPIC-5 CMOS Process  
TFP201A Incorporates HSYNC Jitter  
3
D
D
Skew Tolerant Up to One Pixel Clock Cycle  
4x Over-Sampling  
Immunity  
description  
The Texas Instruments TFP201 and TFP201A are TI PanelBus flat panel display products, part of a  
comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors  
and digital projectors, the TFP201/201A finds applications in any design requiring high-speed digital interface.  
The TFP201/201A supports display resolutions up to SXGA in 24-bit true color pixel format. The TFP201/201A  
offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option  
for time staggered pixel outputs for reduced ground bounce.  
PowerPAD advanced packaging technology results in best of class power dissipation, footprint, and ultra-low  
ground inductance.  
The TFP201/201A combines PanelBus circuit innovation with TI’s advanced 0.18-µm EPIC-5 CMOS  
process technology, along with TI PowerPAD package technology to achieve a reliable, low-powered, low  
noise, high-speed digital interface solution.  
AVAILABLE OPTIONS  
PACKAGED DEVICE  
T
A
100-TQFP  
(PZP)  
TFP201PZP  
0°C to 70°C  
TFP201APZP  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
1. The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for  
high-speed digital connection to digital displays The TFP201 and TFP201A are compliant to the DVI Specification Rev. 1.0.  
2. The TFP201/201A has an internal voltage regulator that provides the 1.8-V core power supply from the externally supplied 3.3-V  
supplies.  
3. The TFP201A incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on  
the transmitted HSYNC signal.  
PanelBus, PowerPAD and EPIC-5 are trademarks of Texas Instruments.  
2
I C is a licensed bus protocol from Phillips Semiconductor, Inc.  
Copyright 2000, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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