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TFB2010MHSB PDF预览

TFB2010MHSB

更新时间: 2024-11-21 20:10:43
品牌 Logo 应用领域
德州仪器 - TI 外围集成电路
页数 文件大小 规格书
10页 121K
描述
SPECIALTY MICROPROCESSOR CIRCUIT, CQFP100, CERAMIC, QFP-100

TFB2010MHSB 技术参数

是否无铅: 含铅生命周期:Obsolete
零件包装代码:QFP包装说明:QFF,
针数:100Reach Compliance Code:unknown
HTS代码:8542.31.00.01风险等级:5.84
JESD-30 代码:R-GQFP-F100长度:20 mm
端子数量:100最高工作温度:70 °C
最低工作温度:封装主体材料:CERAMIC, GLASS-SEALED
封装代码:QFF封装形状:RECTANGULAR
封装形式:FLATPACK认证状态:Not Qualified
座面最大高度:2.7 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:FLAT
端子节距:0.65 mm端子位置:QUAD
宽度:14 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

TFB2010MHSB 数据手册

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TFB2010  
FUTUREBUS+ ARBITRATION BUS CONTROLLER  
SLLS125A – OCTOBER 1990 – REVISED NOVEMBER 1993  
Supports Distributed Arbitration for  
Futurebus+ Master Selection  
Supports Distributed-Mode Bus Parking to  
Improve Performance of Successive Bus  
Acquisitions By a Single Module During  
Idle Bus Conditions  
Supports Arbitrated Messages in  
Distributed and Central Modes  
Offers Accurate Arbitration Settling Time  
and Glitch Filter Programmability to Allow  
Optimal Arbitration Bus Performance  
Enables Use of a Common Hardware and  
Software Interface for Both Distributed and  
Central Modes  
Provides a FIFO for Capturing up to Four  
Incoming Arbitrated Messages  
Requires No Hardware Modifications for  
Changing Between Distributed and Central  
Modes  
Provides Hardware Support of Targeted  
Interrupts  
Provides a CSR Bus Interface for Easy  
Integration into the Futurebus+ CSR  
Address Space  
Supports Power-Fail Message Indication  
With a Separate Terminal and Interrupt  
Has Two Bus Request Lines That Each May  
Be Assigned Any One of 256 Priority Levels  
Provides On-Chip Error Time-Out Detection  
Has a JTAG Test Port  
Supports Round-Robin Fairness Arbitration  
Within Two Separate Priority Levels to  
Avoid Starvation of Any Single Module  
description  
The TFB2010 arbitration bus controller (ABC) is a member of the Texas Instruments Futurebus+ chip set. This  
chip set provides an integrated approach to the Futurebus+ interface that reduces new-product design time,  
allowsmorefunctionalitypercircuitboard, improvesoverallinterfacereliability, andreducesend-userdowntime  
through built-in test capabilities.  
The TFB2010 performs the Futurebus+ distributed-arbitration protocol to gain tenure of the bus (distributed  
mode only), to send and receive arbitrated messages (central or distributed mode), and to update central-mode  
arbiter priorities (central mode only).  
The TFB2010 can be used in conjunction with a central-bus arbiter as an arbitrated-message controller to  
program the central-bus arbiter, send asynchronous interrupts, or send event messages or interrupts to other  
modules. In the case of a failure in the central-bus arbiter or if distributed arbitration is desired, it can be used  
as a distributed-arbitration controller without a change in the host software. Priority changes are sent to the  
central arbiter as arbitrated messages. This device monitors the bus for arbitration messages, storing these in  
a FIFO or in the targeted interrupt register for reference by the processor. It also provides the necessary control  
functions to gain control of the Futurebus+ for a module attempting to perform a bus transaction when operating  
in the distributed-arbitration mode.  
The TFB2010 is offered in a 100-pin plastic quad flat package (PJM) to enhance interface capability. The  
TFB2010 is characterized for operation over the commercial temperature range of 0°C to 70°C.  
NOTE: To maintain consistency with the notation used in the Futurebus+ standard (IEEE Std 896.1–1991), an active low-signal is denoted herein  
by use of the trailing asterisk (*) on the signal name.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
7–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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