Datasheet > 78Q2250-CGT

78Q2250-CGT

更新时间： 2024-01-25 13:01:21

品牌	Logo	应用领域
东电化 - TDK		ATM 异步传输模式电信信息通信管理电信集成电路
页数	文件大小	规格书
11页	73K
描述
Transceiver, 1-Func, BICMOS, PQFP48, TQFP-48

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技术参数
数据手册

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78Q2250-CGT 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	48
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	JESD-30 代码：	S-PQFP-G48
长度：	7 mm	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.6 mm	表面贴装：	YES
技术：	BICMOS	电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	7 mm	Base Number Matches：	1

78Q2250-CGT 数据手册

78Q2250

155 Mbit/s ATM

Line Transceiver

February 1998

Advanced Information

March 1998

DESCRIPTION

FEATURES

The 78Q2250 is a high-speed line transceiver

integrated circuit intended for use in Asynchronous

Transfer Mode (ATM) applications. It is used at the

interface to Category 5 Unshielded Twisted-Pair

(UTP) cabling for distances up to 100 meters, and is

connected to the line via isolation transformers.

Optionally, a PECL interface is provided for use with

an optical interface device. Interface to digital framer

circuits is accomplished via 8-bit parallel CMOS I/O

running at 19.44 Mbit/s.

•

155.52 Mbit/s interface for Category

Unshielded Twisted Pair (UTP) cable

Compliant with ATM PMD

specification for 155.52 Mbit/s over Twisted

Pair Cable

interface

•

Parallel CMOS logic interface at 19.44 Mbit/s

PECL interfaces for connection to fiber optic

receive and transmit modules

The IC provides full transmit and receive line

•

Automatic gain adaptive equalization

Baseline wander correction

interface

functions

with

minimum

external

components required. The receiver provides

adaptive equalization for accurate clock and data

recovery. The 78Q2250 is built in a BiCMOS

technology for highest performance and low power

operation, and is housed in a 48-Pin TQFP package.

Receive clock and data recovery

Advanced BiCMOS process

BLOCK DIAGRAM

UTPOUTP

UTPOUTN

ECLOUTP

PARALLEL

TXD[0:7]

TO SERIAL

PHASE AND

FILTER

ECLOUTN

UTP/

FREQUENCY

÷8

TXCLK

VCO

DETECTOR

XT2

XT1

CRYSTAL

OSCILLATOR

LOCK

DETECTOR

LOCK

155 MHz

CKIN

÷8

RXCLK

TXLB

ECLINP

ECLINN

FILTER

ADAPTIVE

VCO

EQUALIZER

FREQUENCY

DISCRIMINATOR

UTPINP

UTPINN

SERIAL TO

PARALLEL

BASELINE

WANDER

SIGNAL

DATA

RXD[0:7]

DETECTOR

CORRECTION

RETIMING

12 3 4 5 6 7...11

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