78P7200
DS-3/E3/STS-1 Line Interface
With Receive Equalizer
March 1998
DESCRIPTION
FEATURES
The 78P7200 is a line interface transceiver IC
intended for STS-1 (51.84 Mbit/s), DS-3 (44.736
Mbit/s) and E3 (34.368 Mbit/s) applications. The
receiver has a very wide dynamic range and is
designed to accept either HDB3 or B3ZS-encoded
Alternate-Mark Inversion (AMI) inputs; it provides
CMOS logic level clock, positive data, negative data
and low-level signal detector outputs. An on-chip
equalizer improves the intersymbol interference
tolerance on the receive path. The transmitter
converts CMOS logic level clock, positive data and
negative data input signals into AMI pulses of the
appropriate shape for transmission. A line buildout
(LBO) equalizer may be selected to shape the
outgoing pulses for shorter line lengths. The
78P7200 requires a single 5 volt supply and is
available in a surface mount package.
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Single chip transmit and receive interface for
STS-1 (51.84 Mbit/s), E3 (34.368 Mbit/s) or DS-3
(44.736 Mbit/s) applications
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On-chip Receive Equalizer
Unique clock recovery circuit, requires no
crystals, tuned components or external clock
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Selectable transmit line buildout (LBO) to
accommodate shorter line lengths
Compliant with ANSI T1.102-1993, Bellcore TR-
NWT-000499 and GR-253-CORE, ITU-T G.703
and G.823_1991
Low-level input signal indication
Available in a 28 PLCC surface mount package
-40°C to +85°C operating range
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Pin-compatible replacement for 78P236,
The 78P7200 works in either rate of STS-1, DS-3 or
E3 by simple external components modification.
78P2361 and 78P2362
BLOCK DIAGRAM
RVcc
RVcc
CPD
RLF2 RLF1
CLF1
RVcc
Low-Level Signal
Detection
Clock Recovery
RFO
RCLK
DVcc
LIN+
LIN-
RPOS
RNEG
Signal
Acquisition
Data
Detection
Eq.
INPUT
DGND
TVcc
Output
Driver,
Line
Pulse
Shaper
Pulse
Generator
TCLK
LOUT+
LOUT-
TPOS
TNEG
OUTPUT
Buildout
LBO