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78P2342-IEL PDF预览

78P2342-IEL

更新时间: 2024-02-17 22:26:46
品牌 Logo 应用领域
东电化 - TDK PC电信电信集成电路
页数 文件大小 规格书
36页 366K
描述
PCM Transceiver, 1-Func, PQFP100, LQFP-100

78P2342-IEL 技术参数

生命周期:Active零件包装代码:QFP
包装说明:HLFQFP,针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.56JESD-30 代码:S-PQFP-G100
长度:14 mm功能数量:1
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HLFQFP封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.6 mm标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:PCM TRANSCEIVER
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

78P2342-IEL 数据手册

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78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
PRELIMINARY DATASHEET  
JULY 2003  
DESCRIPTION  
FEATURES  
The 78P2342JAT is  
a
low-power, 2-port  
Transmit and receive interfaces for E3, DS3 and  
DS3/E3/STS1 Line Interface Unit (LIU) with  
integrated Jitter Attenuator (JAT). It includes clock  
recovery and transmitter pulse shaping functions for  
applications using 75-ohm coaxial cable at distances  
up to 1350 feet. These applications include  
DSLAMs, T1,3/E1,3 digital multiplexers, SONET  
Add/Drop multiplexers, PDH equipment, DS3 to  
Fiber optic and microwave modems and ATM WAN  
access for routers and switches.  
STS-1 applications  
Designed for use with 75 ohm coaxial cable up  
to 1350 ft long end-to-end or up to 900 ft long  
from a DS3 cross-connect  
Receives DS3-high and DSX3 monitor signals  
Local and Remote loopback  
Selectable B3ZS/HDB3 ENDEC with line code  
violation detector  
Standards-based LOS function  
Optional serial-port based mode selection and  
channel status monitoring  
The receiver recovers clock and data from a B3ZS  
or HDB3 coded AMI signal. It can compensate for  
over 12dB of cable and 6dB of flat loss. The  
transmitter generates a signal that meets the  
Receiver AGC corrects for up to 6dB of flat loss  
Adaptive digital clock recovery (uses line-rate  
reference clock input)  
standard pulse shape requirements.  
It has a  
B3ZS/HDB3 ENDEC with a receive line code  
violation detector, a loop-back mode, an input  
receive MUX that can select a redundant channel, a  
clock polarity selection mode, and the ability to  
receive a DSX3 monitor signal.  
Receive output clock maintains nominal line-rate  
frequency at all times  
Fully integrated Jitter Attenuation function  
provided for all line rates (no external VCXO  
required)  
Jitter Attenuator configurable for transmit or  
receive path  
STANDARDS  
Jitter Tolerance: Telcordia GR-499-CORE [DS3]  
and GR-253-CORE [STS1], ITU-T G.823 [E3]  
and G.824 [DS3]  
Transmit line fault monitor  
Requires no external current-setting resistor or  
loop filter components  
Loss of Signal: ITU-T G.775  
Single 3.3V supply operation  
Jitter Transfer: ETSI TBR-24 1997 [E3];  
Telcordia GR-499-CORE [DS3] and GR-253-  
CORE [DS3/STS1]  
Available in 100-pin Exposed Pad JEDEC LQFP  
BLOCK DIAGRAM  
Controls Flags  
RLBK  
LBO E3 DS3  
Transmit  
TXNW  
TXEN  
Monitor  
TPOS  
TNEG  
TCLK  
B3ZS /  
HDB3  
LOUTP  
LOUTN  
Pulse  
Shaper  
Encoder  
Attenuator  
Jitter  
ENDEC  
Attenuator  
RPOS  
LINP  
LINN  
B3ZS /  
AGC  
Data  
Detector  
Adaptive  
Equalizer  
HDB3  
RNEG  
RCLK  
Decoder  
MON  
TCLKP  
RCLKP  
Power  
Distribution  
Signal  
Detector  
Clock  
Recovery  
LOS  
LLBKA  
LLBKB  
PDTX PDRX  
CKREF  
Signals from  
Adjacent Port  
Each Channel  
CS  
SCK  
SDI  
Master  
Bias  
Generator  
Control  
Registers  
CKREF  
SDO  
- 1 -  

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