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78P2341JAT-IH/F PDF预览

78P2341JAT-IH/F

更新时间: 2024-02-02 17:33:27
品牌 Logo 应用领域
东电化 - TDK PC电信电信集成电路
页数 文件大小 规格书
37页 402K
描述
PCM Transceiver, 1-Func, PQCC28, LEAD FREE, PLASTIC, LCC-28

78P2341JAT-IH/F 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ,针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.77JESD-30 代码:S-PQCC-J28
长度:11.54 mm功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER认证状态:Not Qualified
座面最大高度:4.572 mm标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:PCM TRANSCEIVER
温度等级:INDUSTRIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:11.54 mmBase Number Matches:1

78P2341JAT-IH/F 数据手册

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78P2341JAT  
E3/DS3/STS-1 LIU  
with Jitter Attenuator  
PRELIMINARY DATASHEET  
AUGUST 2003  
DESCRIPTION  
FEATURES  
The 78P2341JAT is a low-power, single channel  
DS3/E3/STS1 transceiver IC with integrated Jitter  
Attenuator (JAT). It includes clock recovery and  
transmitter pulse shaping functions for applications  
using 75-ohm coaxial cable at distances up to 1350  
feet. These applications include DSLAMs, T1,3/E1,3  
digital multiplexers, SONET Add/Drop multiplexers,  
PDH equipment, DS3 to Fiber optic and microwave  
modems, and ATM WAN access for routers and  
switches.  
The receiver recovers clock and data from a B3ZS  
or HDB3 coded AMI signal. It can compensate for  
over 12dB of cable and 6dB of flat loss. The  
transmitter generates a signal that meets the  
standard pulse shape requirements. It has an  
integrated B3ZS/HDB3 ENDEC with a receive line  
code violation detector, a loop-back mode, a clock  
polarity selection mode, and the ability to receive a  
DSX3 monitor signal.  
Transmit and receive interface for E3, DS3 and  
STS-1 applications  
Designed for use with 75 ohm coaxial cable up  
to 1350 ft long end-to-end or up to 900 ft long  
from a DS3 cross-connect  
Receive DS3-high and DSX3 monitor signals  
Local and Remote loopback  
Selectable B3ZS/HDB3 ENDEC with line code  
violation detector  
Standards-based LOS function  
Optional serial-port based mode selection and  
channel status monitoring  
Receiver AGC corrects for up to 6dB of flat loss  
Adaptive digital clock recovery (uses line-rate  
reference clock input)  
Receive output clock maintains nominal line-rate  
frequency at all times  
Fully integrated Jitter Attenuator (no external  
VCXO required) configurable for transmit or  
receive path  
STANDARDS  
Transmit line fault monitor  
Jitter Tolerance: Telcordia GR-499-CORE [DS3]  
and GR-253-CORE [STS1], ITU-T G.823 [E3]  
and G.824 [DS3]  
Requires no external current-setting resistor or  
loop filter components  
Single 3.3V supply operation  
Loss of Signal: ITU-T G.775  
Available in 28-pin PLCC or 48-pin TQFP  
Jitter Transfer: ETSI TBR-24 1997 [E3];  
Telcordia GR-499-CORE [DS3] and GR-253-  
CORE [DS3/STS1]  
BLOCK DIAGRAM  
Controls Flags  
RLBK  
LBO E3 DS3  
Transmit  
TXNW  
TXEN  
Monitor  
TPOS  
TNEG  
B3ZS /  
LOUTP  
LOUTN  
Pulse  
HDB3  
Shaper  
Encoder  
TCLK  
Attenuator  
Jitter  
Attenuator  
ENDEC  
RPOS  
B3ZS /  
HDB3  
Data  
Detector  
Adaptive  
Equalizer  
LINP  
LINN  
RNEG  
RCLK  
AGC  
Decoder  
MON  
TCLKP  
RCLKP  
Power  
Distribution  
Signal  
Detector  
Clock  
Recovery  
LOS  
LLBK  
PDTX PDRX  
CKREF  
Master  
Bias  
Generator  
SCK  
SDIO  
Control  
Registers  
CKREF  
- 1 -  

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