TDA9984A

更新时间： 2024-02-14 21:49:03

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
40页	194K
描述
HDMI 1.3 transmitter with 1080p upscaler embedded

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技术参数
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TDA9984A 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	QFP	包装说明：	12 MM X 12 MM, 1 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT841-4, HTQFP-80
针数：	80	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.69
其他特性：	ALSO REQUIRES 3.3V SUPPLY	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PQFP-G80	长度：	12 mm
功能数量：	1	端子数量：	80
最高工作温度：	85 °C	最低工作温度：	-5 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	HTFQFP
封装等效代码：	TQFP80,.55SQ	封装形状：	SQUARE
封装形式：	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH	电源：	1.8,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	Other Consumer ICs	最大压摆率：	275 mA
最大供电电压 (Vsup)：	1.95 V	最小供电电压 (Vsup)：	1.65 V
表面贴装：	YES	温度等级：	OTHER
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	12 mm
Base Number Matches：	1

TDA9984A 数据手册

TDA9984A

HDMI 1.3 transmitter with 1080p upscaler embedded

Rev. 04 — 15 January 2009

Product data sheet

1. General description

The TDA9984A is a High-Deﬁnition Multimedia Interface (HDMI) v. 1.3 transmitter with

embedded 1080p upscaling functionality. It is backward compatible DVI 1.0 and can be

connected to any DVI 1.0 and HDMI sink. It allows mixing a 3 × 8-bit RGB or YCbCr video

stream with a pixel rate up to 150 MHz together with up to 4 × I²S-bus or one S/PDIF

audio streams with an audio sampling rate up to 192 kHz. It supports Gamut boundary

description (xvYCC), as well as HD audio, both HDMI 1.3 features.

A programmable upscaling block allows creating a 1080p output from a standard deﬁnition

input. An intraﬁeld deinterlacer is included in the scaler.

In order to be compatible with most applications, and thanks to the integration of a fully

programmable input formatter and color space conversion block, the video input formats

accepted also include YCbCr 4 : 4 : 4 (up to 3 × 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to

2 × 12-bit) and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1 × 12-bit). In case of

ITU656-like format, the input pixel clock can be made active on both edges.

The TDA9984A includes a HDCP 1.2 compliant cipher block. The HDCP key are stored

internally in a non-volatile OTP memory for maximum security.

The TDA9984A includes a true I²C-bus master interface for DDC-bus communication for

EDID purpose and HDCP purpose.

The TDA9984A can be controlled by an I²C-bus interface.

2. Features

I 3 × 8-bit video data input buses; CMOS and LV-TTL compatible

I Horizontal synchronization, vertical synchronization and data enable inputs or VREF,

HREF and FREF inputs which can be used for synchronization

I Pixel rate clock input can be made active on one or both edges; selectable via I²C-bus

I 4 × I²S-bus audio input channels, one S/PDIF channel; audio data rate up to 192 kHz

per input for both standards

I Dolby-True HD and DTS-HD High bit rate audio support through the use of the HBR

interface

I 250 MHz to 1.50 GHz TMDS transmitter operation

I Programmable input formatter and upsampler/interpolator allows input of any of the

4 : 4 : 4 or 4 : 2 : 2 semi-planar and 4 : 2 : 2 ITU656-like formats

12 3 4 5 6 7...40

中文翻译

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与TDA9984A相关器件

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TDA9984AHW	NXP	获取价格	HDMI 1.3 transmitter with 1080p upscaler embedded
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