Datasheet > TDA8026ET

TDA8026ET

更新时间： 2024-11-21 15:19:35

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
61页	712K
描述
Multiple smart card slot interface

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TDA8026ET 数据手册

TDA8026

Multiple smart card slot interface IC

Rev. 1.1 — 30 June 2016

Product data sheet

1. General description

The TDA8026 is a cost-effective, analog interface for addressing multiple smart card slots

in a Point Of Sales (POS) terminal. It can address up to two main cards (synchronous or

asynchronous smart cards supported) and up to four Security Access Modules (SAMs).

Its packaging supports the latest payment terminal security requirements.

2. Features and benefits

 I²C-bus controlled IC card interface in a TFBGA64 package

 Supply voltage between 2.7 V and 5.5 V

 Dedicated microcontroller interface supply voltage (V_DD(INTF)

)

 Shutdown mode ensures very low power consumption when the TDA8026 is inactive

 Programmable power reduction modes triggered when the card slots are inactive

 V_CC(n)generation via DC-to-DC converter: two card slots can be fully loaded, the three

others in reduced consumption mode

 Two clock input pins: CLKIN1 for card slot 1 and CLKIN2 for card slots 2 to 5

 Two transparent I/O lines on microcontroller side, one for card slot 1 and the other for

card slots 2 to 5

 Five protected, half-duplex, bidirectional, buffered I/O lines with current limitation at

 15 mA and a maximum frequency 1 MHz

 Two I²C-bus controlled auxiliary I/O lines

 V_CC(n)regulation on all card slots at I_CC 55 mA:

 5 V, 3 V or 1.8 V  5 %

 Current spikes of 40 nAs up to 20 MHz for 5 V cards with controlled rise and fall

times

 Current limitation of approximately 100 mA

 Thermal protection and short-circuit protection on all card contacts

 Automatic activation and deactivation sequences initiated by the software or hardware

in the event of a short-circuit, card take-off or voltage drop-out for V_DD(INTF), V_DDor V_UP

 Enhanced ElectroStatic Discharge (ESD) protection on the card-side up to 6 kV

 20 MHz clock input

 Card clock generation up to 20 MHz and dividable by 1, 2, 4 or 5 with synchronous

frequency changes:

 Stop, HIGH or LOW

 Clock frequency between 1 MHz and 2.2 MHz in card low-power mode

 Current limitation on pin CLK_(n)

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