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TDA7500

更新时间： 2024-11-15 22:53:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 消费电路商用集成电路
页数 文件大小 规格书
14页 155K
描述
DIGITAL AM/FM SIGNAL PROCESSOR

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中文翻译

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TDA7500 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：HLFQFP, QFP100,.63SQ,20针数：100
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.67Is Samacsys：N
商用集成电路类型：CONSUMER CIRCUITJESD-30 代码：S-PQFP-G100
JESD-609代码：e4长度：14 mm
功能数量：1端子数量：100
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HLFQFP
封装等效代码：QFP100,.63SQ,20封装形状：SQUARE
封装形式：FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm子类别：Other Consumer ICs
最大压摆率：490 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.15 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

TDA7500 数据手册

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TDA7500  
®
DIGITAL AM/FM SIGNAL PROCESSOR  
PRODUCT PREVIEW  
FULL SOFTWARE FLEXIBILITY WITH TWO  
24X24 BIT DSP CORES  
AM/FM PROCESSING  
AUDIO-PROCESSING AND SOUND-PROC-  
ESSING  
HARDWARE RDS FILTER, DEMODULATOR  
& DECODER  
INTEGRATED CODEC  
IIC AND SPI CONTROL INTERFACES  
SPI DEDICATED TO DISPLAY MICRO  
6 CHANNEL SERIAL AUDIO INTERFACE SAI  
SPDIF RECEIVER WITH SAMPLE RATE  
CONVERTER  
EXTERNAL MEMORY INTERFACE  
DOUBLE DEBUG INTERFACE  
ON-CHIP PLL  
5V-TOLERANT 3V I/O INTERFACE  
MULTIFUNCTION GENERAL PURPOSE I/O PORTS  
TQFP100 Power with Slug Down  
DESCRIPTION  
The TDA7500 is an integrated circuit implement-  
ing a fully digital, integrated and advanced solu-  
tion to perform the signal processing in front of  
the power amplifier and behind the AM/FM tuner  
or any other audio sources. The chip integrates  
two 43 MIPs DSP cores: one for stereo decoding,  
noise blanking, weak signal processing and multi-  
BLOCK DIAGRAM  
supply  
2
Cref  
2
Mute  
RefOut  
SigGnd  
VS  
3
analog audio in  
1
2
3
4
2
3
1
AM-IF  
CC  
AM  
Noise  
Detector  
IIC  
Output  
select.  
CD  
Input Multiplexer,  
Analog Level Adjust  
Analog Volume Control,  
Line Driver  
6
tel,navi  
signal/line out  
AM/FM lev.  
AM/FM mpx  
RDS mpx  
2 channel analog bypass  
CODEC-ref  
DAC-ref  
6
VDD GND  
3
4
2
Voltage  
Ref.  
Σ∆  
Σ∆  
Σ∆  
Σ∆  
Modulator  
Modulator  
Modulator  
Modulator  
Decimation  
Filter  
SC Filter  
SC Filter  
SC Filter  
SC Filter  
SC Filter  
SC Filter  
Noise  
Shaper  
Oversampling  
Filter  
Decimation  
Filter  
Oversampling  
Filter  
Noise  
Shaper  
Codec  
Ctl Reg.  
Test I/F  
Noise  
Shaper  
Oversampling  
Filter  
uP control  
Main micro  
(4 I/O's)  
4
IIC / SPI  
SPI  
Display uP(4 I/O's)  
4
Spectrum Analyser  
X bus 1  
X bus 0  
X Register  
Ram 512  
X Register  
Ram 512  
Audio Bus Synch.  
CLK in  
8.55MHz  
Data, ctl  
128k (4M) x 8  
Address (1 I/O)  
Audio Bus 6 ch.  
XTAL Osc.,  
PLL  
Y Register  
Ram 512  
Y Register  
Ram 512  
8+3  
17  
Ext. Memory  
Interface  
Exchange  
Interface  
Program  
Ram 1024  
Rom 256  
Program  
Ram 5632  
Rom 256  
3
4
2
dig. aud. out  
(2 I/O's)  
Serial Audio  
Interface  
clkt, wst, clkr, wsr  
1 stereo channel  
dig. aud. in (2 I/O's)  
DSP Orpheus Core  
DSP Orpheus Core  
Int  
Reset  
CD input  
CDC input  
MD input  
Sample Rate  
Converter  
SPDIF  
Interface  
Mux  
including 12 GPIO• s  
including 12 GPIO• s  
FM processing,  
AM processing,  
Traffic mem., Dolby,  
Speech synth., etc...  
Audio processing,  
Sound processing  
5
5
2
4
4
VDD  
GND  
(1 I/O)  
RDS bit/blk Int.  
RDS  
Grp & blk  
sync., error  
correction  
4
Test  
(3 I/O's)  
(3 I/O's)  
RDS  
Demod.  
(4 I/O's)  
SPI  
Debug, Test Interface  
Debug, Test Interface  
Filter  
Error corrected RDS blocks  
alternatively:  
RDS clk, dat, qual, ARI  
DSP1  
DSP0  
RDS  
September 1999  
1/14  
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.  
1234567...14

中文翻译

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