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TDA7463D013TR PDF预览

TDA7463D013TR

更新时间: 2024-11-15 22:13:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
12页 116K
描述
LOW VOLTAGE TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR

TDA7463D013TR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SO-16
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.73信道分离:80 dB
商用集成电路类型:TONE CONTROL CIRCUITJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:10.3 mm
湿度敏感等级:3频带数量:2
信道数量:2功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:2.4 V
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Audio Control ICs最大供电电压 (Vsup):3 V
最小供电电压 (Vsup):1.8 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

TDA7463D013TR 数据手册

 浏览型号TDA7463D013TR的Datasheet PDF文件第2页浏览型号TDA7463D013TR的Datasheet PDF文件第3页浏览型号TDA7463D013TR的Datasheet PDF文件第4页浏览型号TDA7463D013TR的Datasheet PDF文件第5页浏览型号TDA7463D013TR的Datasheet PDF文件第6页浏览型号TDA7463D013TR的Datasheet PDF文件第7页 
TDA7463D  
LOW VOLTAGE TONE CONTROL  
DIGITALLY CONTROLLED AUDIO PROCESSOR  
1 FEATURES  
Figure 1. Package  
1 STEREO INPUT  
1 STEREO OUTPUT  
TREBLE BOOST  
BASS CONTROL  
SO16  
BASS AUTOMATIC LEVEL CONTROL  
VOLUME CONTROL IN 1dB STEPS  
MUTE  
Table 1. Order Codes  
Part Number  
TDA7463D  
Package  
SO16  
STAND-BY FUNCTION SOFTWARE  
TDA7463D013TR  
Tape & Reel  
CONTROLLED  
ALL FUNCTION ARE PROGRAMMABLE VIA  
SERIAL BUS  
the functions is accomplished by serial bus.  
The AC signal setting is obtained by resistor net-  
works and switches combined with operational  
amplifiers. Thanks to the used BIPOLAR/CMOS  
Technology,  
2 DESCRIPTION  
The TDA7463 is a volume tone (bass and treble)  
processor for quality audio applications in Low  
voltage supply portable systems.  
Low Distortion, Low Noise and DC stepping are  
obtained.obtained.  
Bass ALC (Automatic Level Control) function can  
be adjusted by a dedicated pin. The control of all  
Figure 2. Block Diagram  
R5  
5.6K  
C12 3.3nF  
100nF  
100nF  
C11  
C10  
TREBLE-R  
BASSI-R  
BASSO-R  
RB  
-63dB  
CONTROL  
0/-10dB  
C1 0.47µF  
x1  
x5  
OUT-R  
IN-R  
TREBLE  
BASS  
50K  
2
I C  
V
V
S
S
BASS_ALC  
CONTROL  
1
VS  
R3  
1KΩ  
R4  
1KΩ  
2
3
DGND  
SCL  
SDA  
C2 0.47µF  
SCL  
SDA  
ALC  
HALF_WAVE  
RECTIFIER  
2
I C BUS DECODER + LATCHES  
+
4
R1  
1MΩ  
C3 0.47µF  
x5  
OUT-L  
IN-L  
TREBLE  
BASS  
x1  
50K  
-63dB  
0/-10dB  
CONTROL  
V
S
SUPPLY  
GND  
V
S
RB  
VREF  
C8  
100nF  
C9  
100µF  
TREBLE-L  
BASSI-L  
BASSO-L  
CREF  
D96AU482B  
C5  
100nF  
C6  
100nF  
C4  
3.3nF  
C7  
22µF  
R2  
5.6K  
REV. 4  
1/12  
June 2004  

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