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TDA19978AHV PDF预览

TDA19978AHV

更新时间: 2024-01-16 13:41:59
品牌 Logo 应用领域
恩智浦 - NXP 消费电路商用集成电路电视PC
页数 文件大小 规格书
38页 276K
描述
Quad HDMI 1.3a receiver interface with equalizer (HDTV up to 1080p, up to UXGA for PC formats)

TDA19978AHV 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT-612-3, HLQFP-144针数:144
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.82其他特性:IT ALSO REQUIRES 3.135V TO 3.465V DIGITAL SUPPLY
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-PQFP-G144
长度:20 mm功能数量:1
端子数量:144最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP144,.87SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
电源:1.8,3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Other Consumer ICs
最大供电电压 (Vsup):1.89 V最小供电电压 (Vsup):1.71 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:20 mmBase Number Matches:1

TDA19978AHV 数据手册

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TDA19978A  
Quad HDMI 1.3a receiver interface with equalizer (HDTV up to  
1080p, up to UXGA for PC formats)  
Rev. 03 — 16 April 2010  
Product data sheet  
1. General description  
The TDA19978A is a four input HDMI 1.3a compliant receiver with embedded EDID  
memory. The built in auto-adaptive equalizer improves signal quality and allows the use of  
cable lengths up to 25 m (laboratory tested with a 0.5 mm (24 AWG) cable at  
2.05 gigasamples per second). The HDCP key set is stored in non-volatile One Time  
Programmable (OTP) memory for maximum security. In addition, the TDA19978A is  
delivered with software drivers to ease configuration and use.  
The TDA19978A supports:  
TV resolutions:  
480i (1440 × 480i at 60 Hz), 576i (1440 × 576i at 50 Hz) to HDTV (up to  
1920 × 1080p at 50/60 Hz)  
WUXGA (1920 × 1200p at 60 Hz) reduced blanking format  
PC resolutions:  
VGA (640 × 480p at 60 Hz) to UXGA (1600 × 1200p at 60 Hz)  
Deep Color mode in 10-bit and 12-bit (up to 205 MHz TMDS clock)  
Gamut boundary description  
IEC 60958/IEC 61937, One Bit Audio (in SACD), DST (in compressed DSD) and HBR  
stream  
The TDA19978A includes:  
An enhanced PC and TV format recognition system  
Generation of a 128/256/512 × fs system clock allowing the use of simple audio DACs  
without an integrated PLL (such as the UDA1334BTS)  
An embedded oscillator (an external crystal can also be used)  
Improved audio clock generation using an external reference clock  
One Bit Audio (in SACD), DST (in compressed DSD) and HBR stream support  
The TDA19978A converts HDMI streams with or without HDCP into RGB or YCbCr digital  
signals. The YCbCr digital output signal can be 4:4:4 or 4:2:2 semi-planar format based  
on the ITU-R BT.601 standard or 4:2:2 based on the ITU-R BT.656 format. The device can  
adjust the output timing of the video port by altering the values for tsu(Q) and th(Q). In  
addition, all settings are controllable using the I2C-bus.  

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