Datasheet > TC9594XBG

TC9594XBG

更新时间： 2024-11-06 14:56:19

品牌	Logo	应用领域
东芝 - TOSHIBA		/
页数	文件大小	规格书
16页	195K
描述
Automotive IVI

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中文翻译

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数据手册

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TC9594XBG 数据手册

TC9594XBG

CMOS Digital Integrated Circuit Silicon Monolithic

TC9594XBG

Overview

Parallel Port to MIPI^®DSI^SM(TC9594XBG) is a

bridge device that converts RGB to DSI. All

internal registers can be accessed through

I²C or SPI.

P-VFBGA80-0707-0.65-001

Weight: 66 mg (Typ.)

Features

● Power supply inputs

 Core and MIPI^®D-PHY: 1.2V

 I/O: 1.8V or 3.3V

● DSI-TX interface

 MIPI^®DSI compliant (Version 1.02.00– June 28,

2010)

Support DSI Video Mode data transfer

DCS Command for panel register access

● Typical power consumption

 WXGA @60fps: Pixel Clk: 74.25 MHz, DSIClk:

 Supports up to 1 Gbps per data lane

 Supports1,2,3 or 4 data lanes

 Supports video data formats

312 MHz  66.6 mW

 1080P @60fps: Pixel Clk: 148.5 MHz, DSIClk:

471 MHz  91.4 mW

 Power Down Condition is achieved by

turning off clock sources: PClk and RefClk.

RGB888/666/565

● RGB interface

 Supports data formats

24-bit data bus

 RGB888/666/565 data formats

● Operation temperature range

 Ta = -40 °C to 105 °C

 Up to 166 MHz input clock

 Support VSYNC/HSYNC polarity option

(default LOW)

 Support DE polarity option (default High)

● AEC-Q100 qualified with the following definition



Grade 2 : -40 °C to 105 °C ambient

operating temperature range

● I²C/SPI Slave Interface (Option to select either I²C

or SPI interface)

 I²C Interface (when CS=L)

Support for normal (100KHz), fast mode (400

kHz) and Special mode (1 MHz)

Configure all TC9594XBG internal registers

Writing to DCS registers will trigger DCS

Command transmits over DSI

 SPI interface (when CS =H)

SPI interface support for up to 25 MHz

operation.

Configure all TC9594XBG internal registers

Writing to DCS registers will trigger DCS

Command transmits over DSI

● GPIO signals

 2 GPIO signals

Two GPIO signals can be configured as SPI

signals (SPI_SS and SPI_MISO)

Or one GPIO signal can be configured as

Interrupt output signal, INT.

● System

 Clock and power management support to achieve

low power states.

Toshiba Electronic Devices & Storage Corporation

1 / 16

2020-04-06

Rev. 1.0

12 3 4 5 6 7...16

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