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TC9593XBG PDF预览

TC9593XBG

更新时间: 2024-11-22 14:58:15
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
24页 661K
描述
Automotive IVI

TC9593XBG 数据手册

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TC9592XBG/TC9593XBG  
CMOS Digital Integrated Circuit Silicon Monolithic  
TC9592XBG/TC9593XBG  
Automotive Peripheral Devices  
TC9592XBG  
Overview  
The TC9592XBG/TC9593XBG Functional Specification defines  
operation of the DSISM to LVDS low power chip.  
TC9592XBG/TC9593XBG is the follow-up chip of TC358764XBG/  
TC358765XBG, which:  
P-VFBGA49-0505-0.65-001  
Weight: 39 mg (Typ.)  
1. Exhibit LVDS Tx block operates at 1.8V @135 MHz to reduce  
operation power  
TC9593XBG  
2. Update 4-lane DSI Rx max bit rate @ 1 Gbps/lane to support  
1920×1200×24 @60fps  
3. Add STBY pin with to enable turning on VDDIO power first before  
other power supplies.  
P-VFBGA64-0606-0.65-001  
Weight: 55 mg (Typ.)  
The primary function of this chip is DSI-to-LVDS Bridge, enabling  
video streaming output over DSI link to drive LVDS-compatible  
display panels. The chip supports up to 1600×1200 24-bits per pixel resolution for single-link LVDS and  
up to WUXGA (1920×1200 24-bits pixels) resolution for dual-link LVDS. As a secondary function, the  
chip also supports an I2C Master which is controlled by the DSI link; this may be used as an interface to  
any other control functions through I2C.  
Features  
DSI Receiver  
Configurable 1- up to 4-Data-Lane DSI Link with  
Supports display up to 1600×1200 24-bits per  
pixel resolution for single-link, or up to 1920×1200  
24-bits resolutions for dual-link  
bi-directional support on Data Lane 0  
Supports the following pixel formats:  
- RGB666 18-bits per pixel  
- RGB888 24-bits per pixel  
Features Toshiba Magic Square algorithm which  
enables a RGB666 display panel to produce a  
display quality almost equivalent to that of an  
RGB888 24-bits panel  
Maximum bit rate of 1 Gbps/lane  
Video input data formats:  
- RGB565 16-bits per pixel  
- RGB666 18-bits per pixel  
- RGB666 loosely packed 24-bits per pixel  
- RGB888 24-bits per pixel  
Video frame size:  
Flexible mapping of parallel data input bit ordering  
Supports programmable clock polarity  
Supports two power saving states  
- Up to 1600×1200 24-bits per pixel resolution to  
single-link LVDS display panel, limited by 135  
MHz LVDS speed  
- Sleep state, when receiving DSI ULPS signaling  
- Standby state, entered by STBY pin assertion  
- Up to WUXGA resolutions (1920×1200 24-bits  
pixels) to dual-link LVDS display panel, limited by  
4 Gbps DSI link speed  
System Operation  
Supports Video Stream packets for video data  
Host configures the chip through DSI link  
transmission.  
Through DSI link, Host accesses the chip register  
set using Generic Write and Read packets. One  
Generic Long Write packet can write to multiple  
contiguous register addresses  
Includes an I2C Master function which is controlled  
by Host through DSI link (multi-master is not  
supported)  
Supports generic long packets for accessing the  
chip's register set  
Supports the path for Host to control the on-chip  
I2C Master  
LVDS FPD Link Transmitter  
Supports single-link or dual-link  
Maximum pixel clock frequency of 135 MHz.  
Maximum pixel clock speed of 135 MHz for single-  
Power management features to save power  
Configuration registers is also accessible through  
I2C Slave interface  
link or 270 MHz for dual-link  
© 2014-2022  
Toshiba Electronic Devices & Storage Corporation  
1 / 24  
2022-05-25  
Rev 1.2  

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