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TC80C251TQ24 PDF预览

TC80C251TQ24

更新时间: 2024-09-27 08:10:03
品牌 Logo 应用领域
英特尔 - INTEL 微控制器
页数 文件大小 规格书
34页 238K
描述
Microcontroller, 8-Bit, CMOS, CDIP40, CERAMIC, DIP-40

TC80C251TQ24 数据手册

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ADVANCE INFORMATION  
8xC251TA/TB/TP/TQ  
HIGH-PERFORMANCE CHMOS MICROCONTROLLER  
Commercial/Express  
Real-time and Programmed Wait State  
User-selectable Configurations:  
Bus Operation  
— External Wait States (0-3 wait  
states)  
— Address Range & Memory Mapping  
— Page Mode  
— Extended Data Float Timings or  
8xC251Sx Compatible AC Timings  
®
Binary-code Compatible with MCS 51  
Pin Compatible with 44-pin PLCC and  
40-pin PDIP MCS 51 Sockets  
®
Register-based MCS 251 Architecture  
— 40-byte Register File  
— Registers Accessible as Bytes,  
Words, or Double Words  
32 Programmable I/O Lines  
Eight Maskable Interrupt Sources with  
Four Programmable Priority Levels  
Enriched MCS 51 Instruction Set  
Three Flexible 16-bit Timer/counters  
Hardware Watchdog Timer  
— 16-bit and 32-bit Arithmetic and  
Logic Instructions  
— Compare and Conditional Jump  
Instructions  
— Expanded Set of Move Instructions  
Programmable Counter Array  
— High-speed Output  
— Compare/Capture Operation  
— Pulse Width Modulator  
— Watchdog Timer  
Linear Addressing  
256-Kbyte Expanded External  
Code/Data Memory Space  
Two Programmable Serial I/O Ports  
— Framing Error Detection  
ROM Options:  
16 Kbytes (TB/TQ), 8 Kbytes (TA/TP), or  
without ROM  
— Automatic Address Recognition  
High-performance CHMOS Technology  
Static Standby to 24-MHz Operation  
16-bit Internal Code Fetch  
64-Kbyte Extended Stack Space  
Complete System Development  
On-chip Data RAM Options:  
Support  
1-Kbyte (TA/TB) or 512-Byte (TP/TQ)  
— Compatible with Existing Tools  
8-bit, 2-clock External Code Fetch in  
— MCS 251 Tools Available:  
Compiler, Assembler, Debugger,  
ICE  
Page Mode  
Fast MCS 251 Instruction Pipeline  
Package Options (PDIP and PLCC)  
© INTEL CORPORATION, 1997  
November, 1997  
Order Number: 273129-001  

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