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TC8020K6-G PDF预览

TC8020K6-G

更新时间: 2024-11-05 21:12:27
品牌 Logo 应用领域
美国微芯 - MICROCHIP 开关晶体管
页数 文件大小 规格书
8页 644K
描述
POWER, FET

TC8020K6-G 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:CHIP CARRIER, S-XQCC-N56Reach Compliance Code:compliant
ECCN代码:EAR99Factory Lead Time:17 weeks
风险等级:1.12配置:COMPLEX
最小漏源击穿电压:200 V最大漏源导通电阻:8 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:S-XQCC-N56
JESD-609代码:e4元件数量:6
端子数量:56工作模式:ENHANCEMENT MODE
封装主体材料:UNSPECIFIED封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
极性/信道类型:N-CHANNEL AND P-CHANNEL表面贴装:YES
端子面层:NICKEL PALLADIUM GOLD端子形式:NO LEAD
端子位置:QUAD处于峰值回流温度下的最长时间:40
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

TC8020K6-G 数据手册

 浏览型号TC8020K6-G的Datasheet PDF文件第2页浏览型号TC8020K6-G的Datasheet PDF文件第3页浏览型号TC8020K6-G的Datasheet PDF文件第4页浏览型号TC8020K6-G的Datasheet PDF文件第5页浏览型号TC8020K6-G的Datasheet PDF文件第6页浏览型号TC8020K6-G的Datasheet PDF文件第7页 
Supertex inc.  
TC8020  
Six Pair, N- and P-Channel  
Enhancement-Mode MOSFET  
Features  
General Description  
High voltage, vertical DMOS technology  
Integrated gate-to-source resistor  
Integrated gate-to-source Zener diode  
Typical peak output +/-3.5A at 50V  
Low threshold, low on-resistance  
Low input & output capacitance  
Fast switching speeds  
The Supertex TC8020 consists of six pairs of high voltage,  
low threshold N- and P-channel MOSFETs in a 56-lead QFN  
package. All MOSFETs have integrated gate-to-source resistors  
and gate-to-source Zener diode clamps which are desired for  
high voltage pulser applications. The complimentary, high-speed,  
high voltage, gate-clamped N- and P-channel MOSFET pairs  
utilize an advanced vertical DMOS structure and Supertex’s well-  
proven silicon-gate manufacturing process. This combination  
produces a device with the power handling capabilities of bipolar  
transistors and with the high input impedance and positive  
temperature coefficient inherent in MOS devices.  
Electrically isolated N- and P-MOSFET pairs  
Applications  
High voltage pulsers  
Amplifiers  
Buffers  
Piezoelectric transducer drivers  
General purpose line drivers  
Logic level interfaces  
Characteristic of all MOS structures, this device is free from  
thermal runaway and thermally-induced secondary breakdown.  
Supertex’s vertical DMOS FETs are ideally suited to a wide  
range of switching and amplifying applications where very  
low threshold voltage, high breakdown voltage, high input  
impedance, low input and output capacitance, and fast switching  
speeds are desired.  
Typical Application  
VPP2  
VPP1  
+3.3V  
+12V  
+12V  
+12V  
VLL/EN  
AVDD  
VDD1  
VDD2  
SP6 SP3 SP5 SP2 SP4  
SP1  
OP1A  
ON1A  
OP2A  
ON2A  
OP3A  
ON3A  
OP1B  
ON2A  
OP2B  
ON2B  
OP3B  
ON3B  
GP1  
GN1  
GP2  
GN2  
GP3  
GN3  
GP4  
GN4  
GP5  
GN5  
GP6  
GN6  
DP1  
DN1  
DP2  
DN2  
DP3  
DN3  
DP4  
DN4  
DP5  
DN5  
DP6  
DN6  
10nF  
10nF  
10nF  
10nF  
TX(A)  
SELA  
POSA  
NEGA  
POSB  
NEGB  
SELB  
1.8 to 3.3V  
CMOS  
Input Logic  
MD1715  
TC8020  
10nF  
10nF  
10nF  
10nF  
TX(B)  
AGND GND AVSS(SUB)  
VSS  
PAD SN6 SN3 SN5 SN2 SN4 SN1  
-12V  
-12V  
VNN2  
VNN1  
Supertex inc.  
Doc.# DSFP-TC8020  
C091112  
www.supertex.com  

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