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TC7WP3125FC PDF预览

TC7WP3125FC

更新时间： 2024-11-16 04:28:43
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
12页 253K
描述
Digital Integrated Circuit Silicon Monolithic Low Voltage/Low Power 2-Bit Dual Supply Bus Buffer

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TC7WP3125FC 技术参数

生命周期：Lifetime Buy零件包装代码：SON
包装说明：HVSON, SOLCC8,.05,16针数：8
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.61其他特性：1.1V TO 2.7V SUPPLY FOR PORT A; 1.65V TO 3.6V SUPPLY FOR PORT B
控制类型：ENABLE LOW系列：P
JESD-30 代码：R-PDSO-N8JESD-609代码：e0
长度：1.45 mm负载电容（CL）：30 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.0001 A
位数：2功能数量：1
端口数量：2端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：HVSON
封装等效代码：SOLCC8,.05,16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE电源：1.2/2.5,1.8/3.3 V
Prop。Delay @ Nom-Sup：30 ns传播延迟（tpd）：30 ns
认证状态：Not Qualified座面最大高度：0.4 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：1.1 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：NO LEAD端子节距：0.4 mm
端子位置：DUAL宽度：1.35 mm
Base Number Matches：1

TC7WP3125FC 数据手册

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TC7WP3125FK/FC  
TOSHIBA Digital Integrated Circuit Silicon Monolithic  
TC7WP3125FK, TC7WP3125FC  
Low Voltage/Low Power 2-Bit Dual Supply Bus Buffer  
The TC7WP3125 is a dual supply, advanced high-speed CMOS  
2-bit dual supply voltage interface bus buffer fabricated with  
silicon gate CMOS technology.  
TC7WP3125FK  
It is also designed with over voltage tolerant inputs and  
outputs up to 3.6 V.  
Designed for use as an interface between a 1.2-V, 1.5-V, 1.8-V,  
or 2.5-V bus and a 1.8-V, 2.5-V or 3.6-V bus in mixed 1.2-V, 1.5-V,  
1.8-V or 2.5-V/1.8-V, 2.5-V or 3.6-V supply systems.  
The A-input interfaces with the 1.2-V, 1.5-V, 1.8-V or 2.5-V bus,  
the B-output with the 1.8-V, 2.5-V, 3.3-V bus.  
TC7WP3125FC  
The enable input (OE) can be used to disable the device so that  
the signal lines are effectively isolated.  
All inputs are equipped with protection circuits against static  
discharge or transient excess voltage.  
Weight:  
SSOP8-P-0.50A : 0.01 g (typ.)  
CSON8-P-0.4 : 0.002 g (typ.)  
Features  
•
Level converter for interfacing 1.2-V to 1.8-V, 1.2-V to 2.5-V, 1.2-V to 3.3-V, 1.5-V to 2.5-V, 1.5-V to 3.3-V, 1.8-V  
to 2.5-V, 1.8-V to 3.3-V or 2.5 V to 3.3-V system.  
•
High-speed operation : t = 6.8 ns (max) (V  
= 2.5 ± 0.2 V, V  
= 1.8 ± 0.15 V, V  
= 3.3 ± 0.3 V)  
pd  
CCA  
CCA  
CCA  
CCA  
CCB  
t
pd  
t
pd  
t
pd  
t
pd  
t
pd  
t
pd  
t
pd  
= 7.8 ns (max) (V  
= 8.6 ns (max) (V  
= 3.3 ± 0.3 V)  
CCB  
= 1.5 ± 0.1 V, V  
= 3.3 ± 0.3 V)  
= 3.3 ± 0.3 V)  
CCB  
CCB  
= 22 ns (max) (V  
= 9.5 ns (max) (V  
= 1.2 ± 0.1 V, V  
= 1.8 ± 0.15 V, V  
= 2.5 ± 0.2 V)  
CCA  
CCB  
= 10.8 ns (max) (V  
= 1.5 ± 0.15 V, V  
= 2.5 ± 0.2 V)  
CCB  
= 2.5 ± 0.2 V)  
= 1.8 ± 0.15 V)  
CCA  
= 23 ns (max) (V  
= 30 ns (max) (V  
= 1.2 ± 0.15 V, V  
CCA  
CCA  
CCB  
= 1.2 ± 0.1 V, V  
CCB  
•
Output current : I /I  
= ±12 mA (min) (V  
= 3.0 V)  
OH OL CC  
I
I
/I  
= ±9mA (min) (V  
= ±3 mA (min) (V  
= 2.3 V)  
= 1.65 V)  
OH OL  
CC  
/I  
OH OL  
CC  
•
•
Latch-up performance: -300 mA  
ESD performance:Machine model ≥ ±200 V  
Human body model ≥ ±2000 V  
•
•
Ultra-small package: CSON8(CST8), SSOP8(US8)  
Low current consumption: Using the new circuit significantly reduces current consumption when OE = “H”.  
Suitable for battery-driven applications such as PDAs and cellular phones.  
•
3.6-V tolerant function and power-down protection provided on all inputs and outputs.  
Note: Do not apply a signal to any bus pins when it is in the output mode. Damage may result.  
1
2007-10-19  
1234567...12

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