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TC7WH02FK,LJ(CT PDF预览

TC7WH02FK,LJ(CT

更新时间: 2024-11-16 12:58:07
品牌 Logo 应用领域
东芝 - TOSHIBA 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 149K
描述
OR GATE

TC7WH02FK,LJ(CT 技术参数

生命周期:Active包装说明:VSSOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.64系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G8长度:2.3 mm
逻辑集成电路类型:OR GATE功能数量:2
输入次数:2端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
传播延迟(tpd):13 ns座面最大高度:0.9 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL宽度:2 mm
Base Number Matches:1

TC7WH02FK,LJ(CT 数据手册

 浏览型号TC7WH02FK,LJ(CT的Datasheet PDF文件第2页浏览型号TC7WH02FK,LJ(CT的Datasheet PDF文件第3页浏览型号TC7WH02FK,LJ(CT的Datasheet PDF文件第4页浏览型号TC7WH02FK,LJ(CT的Datasheet PDF文件第5页 
TC7WH02FC  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC7WH02FC  
Dual 2-Input NOR Gate  
Features  
High-speed  
:t = 3.6ns (Typ.) at V  
= 5 V  
pd  
CC  
TC7WH02FC  
Low power dissipation  
High noise immunity  
Operation voltage range  
5.5-V Tolerant inputs.  
:ICC=2μA(Max.) at Ta=25°C  
:VNIH=VNIL=28%VCC(Min.)  
:VCC(opr.)=2~5.5V  
CSON8-P-0.4  
Weight: 0.002g (typ.)  
Absolute Maximum Ratings ( Ta = 25°C )  
Marking  
Product name  
Characteristics  
Symbol  
Ratingh  
Unit  
Power supply viltage  
DC input voltage  
V
0.5~7.0  
0.5~7.0  
V
CC  
H02  
V
V
IN  
DC output voltage  
Input diode current  
Output diode current  
DC output current  
V
0.5~V  
+ 0.5 (Note1)  
CC  
20  
V
OUT  
I
mA  
(Note2) mA  
mA  
IK  
I
±20  
±25  
OK  
I
OUT  
DC V /GND current  
CC  
I
±50  
150  
mA  
CC  
Pin Assignment (top view)  
Power dissipation  
P
(Note3) mW  
°C  
D
Storage temperature  
T
65~150  
stg  
Vcc  
1Y  
2B  
2A  
Note: Using continuously under heavy loads (e.g. the application of  
high temperature/current/voltage and the significant change in  
temperature, etc.) may cause this product to decrease in the  
reliability significantly even if the operating conditions (i.e.  
operating temperature/current/voltage, etc.) are within the  
absolute maximum ratings and the operating ranges.  
Please design the appropriate reliability upon reviewing the  
Toshiba Semiconductor Reliability Handbook (“Handling  
Precautions”/“Derating Concept and Methods”) and individual  
reliability data (i.e. reliability test report and estimated failure  
rate, etc).  
8
7
6
5
1
2
3
4
1A  
1B  
2Y GND  
Note1 : High or Low State.  
I
absolute maximum rating must be observed.  
OUT  
Note2 : VOUT < GND , VOUT > VCC  
Note3 : Mounted on an FR4 board.  
2
(25.4 mm × 25.4 mm × 1.6 t, Cu Pad: 11.56 mm )  
Truth Table  
IEC Logic Diagram  
Inputs  
Outputs  
Y
1A  
1B  
>
>
A
L
B
L
1
1
1Y  
2Y  
H
L
L
L
L
H
L
2A  
2B  
H
H
H
1
2007-11-01  

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