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TC7MPN3125FTG PDF预览

TC7MPN3125FTG

更新时间： 2024-11-29 04:00:27
品牌 Logo 应用领域
东芝 - TOSHIBA 总线驱动器总线收发器逻辑集成电路
页数 文件大小 规格书
22页 307K
描述
Low Voltage/Low Power 2-Bit 】 2 Dual Supply Bus Transceiver

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中文翻译

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TC7MPN3125FTG 技术参数

生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN, LCC16,.1SQ,20针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.61Is Samacsys：N
其他特性：1.1V TO 2.7V SUPPLY FOR PORT A; 1.65V TO 3.6V SUPPLY FOR PORT B控制类型：COMMON CONTROL
计数方向：BIDIRECTIONAL系列：P
JESD-30 代码：S-PQCC-N16JESD-609代码：e2
长度：2.7 mm逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.0005 A位数：2
功能数量：2端口数量：2
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC16,.1SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
电源：1.2/2.5,1.8/3.3 VProp。Delay @ Nom-Sup：58 ns
传播延迟（tpd）：61 ns认证状态：Not Qualified
座面最大高度：0.6 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：1.1 V
标称供电电压 (Vsup)：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN SILVER端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
翻译：N/A宽度：2.7 mm
Base Number Matches：1

TC7MPN3125FTG 数据手册

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TC7MPN3125FTG  
TOSHIBA Digital Integrated Circuit Silicon Monolithic  
TC7MPN3125FTG  
Low Voltage/Low Power 2-Bit × 2 Dual Supply Bus Transceiver  
The TC7MPN3125FTG is a dual supply, advanced high-speed  
CMOS 4-bit dual supply voltage interface bus transceiver  
fabricated with silicon gate CMOS technology.  
It is also designed with over voltage tolerant inputs and  
outputs up to 3.6 V.  
Designed for use as an interface between a 1.2-V, 1.5-V, 1.8-V,  
or 2.5-V bus and a 1.8-V, 2.5-V or 3.6-V bus in mixed 1.2-V, 1.5-V,  
1.8-V or 2.5-V/1.8-V, 2.5-V or 3.6-V supply systems.  
The A-port interfaces with the 1.2-V, 1.5-V, 1.8-V or 2.5-V bus,  
the B-port with the 1.8-V, 2.5-V, 3.3-V bus.  
The direction of data transmission is determined by the level of  
the DIR input. The enable input ( OE ) can be used to disable the  
device so that the buses are effectively isolated.  
Weight: 0.013 g (typ.)  
All inputs are equipped with protection circuits against static discharge or transient excess voltage.  
Features  
•
Bidirectional interface between 1.2-V and 1.8-V, 1.2-V and 2.5-V, 1.2-V and 3.3-V, 1.5-V and 2.5-V, 1.5-V and  
3.3-V, 1.8-V and 2.5-V, 1.8-V and 3.3-V or 2.5-V and 3.3-V buses.  
•
High-speed operation: t = 13.7 ns (max) (V  
= 2.5 ± 0.2 V, V  
= 1.8 ± 0.15 V, V  
= 3.3 ± 0.3 V)  
= 3.3 ± 0.3 V)  
CCB  
pd  
CCA  
CCA  
CCA  
CCB  
t
pd  
t
pd  
t
pd  
t
pd  
t
pd  
t
pd  
t
pd  
= 14.8 ns (max) (V  
= 16.0 ns (max) (V  
= 1.5 ± 0.1 V, V  
= 3.3 ± 0.3 V)  
CCB  
= 61 ns (max) (V  
= 1.2 ± 0.1 V, V = 3.3 ± 0.3 V)  
CCB  
CCA  
= 18.5 ns (max) (V  
= 19.7 ns (max) (V  
= 1.8 ± 0.15 V, V  
= 1.5 ± 0.15 V, V  
= 2.5 ± 0.2 V)  
= 2.5 ± 0.2 V)  
CCA  
CCA  
CCB  
CCB  
= 60 ns (max) (V  
= 58 ns (max) (V  
= 1.2 ± 0.15 V, V  
= 2.5 ± 0.2 V)  
= 1.8 ± 0.15 V)  
CCA  
CCA  
CCB  
= 1.2 ± 0.1 V, V  
CCB  
•
Output current: I  
/I  
/I  
/I  
/I  
/I  
/I  
= ±3 mA (min) (V  
= ±2 mA (min) (V  
= ±0.5 mA (min) (V  
= 3.0 V)  
= 2.3 V)  
OHB OLB  
CCB  
I
I
I
I
I
OHB OLB  
CCB  
= 1.65 V)  
OHB OLB  
CCB  
= ±9 mA (min) (V  
= ±3 mA (min) (V  
= ±1 mA (min) (V  
= 2.3 V)  
= 1.65 V)  
= 1.4 V)  
OHA OLA  
CCA  
CCA  
CCA  
OHA OLA  
OHA OLA  
•
•
Latch-up performance: ±300 mA  
ESD performance:Machine model ≥ ±200 V  
Human body model ≥ ±2000 V  
•
•
Ultra-small package: VQON16  
Low current consumption: Using the new circuit significantly reduces current consumption when OE = “H”.  
Suitable for battery-driven applications such as PDAs and cellular phones.  
•
Floating A-bus and B-bus are permitted. (when OE = “H”)  
3.6-V tolerant function and power-down protection provided on all inputs and outputs.  
Note 1: Do not apply a signal to any bus pins when it is in the output mode. Damage may result.  
Note: When mounting VQON package, the type of recommended flux is RA or RMA.  
1
2007-10-19  
1234567...22

中文翻译

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