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TC74VHCT373AFK(EL) PDF预览

TC74VHCT373AFK(EL)

更新时间: 2024-11-06 06:47:31
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
9页 178K
描述
IC,LATCH,SINGLE,8-BIT,AHCT/VHCT-CMOS,TSSOP,20PIN,PLASTIC

TC74VHCT373AFK(EL) 数据手册

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TC74VHCT373AF/AFT/AFK  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74VHCT373AF,TC74VHCT373AFT,TC74VHCT373AFK  
Octal D-Type Latch with 3-State Output  
The TC74VHCT373A is an advanced high speed CMOS OCTAL  
LATCH with 3-STATE OUTPUT fabricated with silicon gate  
C2MOS technology.  
It achieves the high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low power  
dissipation.  
This 8-bit D-type latch is controlled by a latch enable input  
(LE) and an output enable input ( OE ).  
When the OE input is high, the eight outputs are in a high  
impedance state.  
The input voltage are compatible with TTL output voltage.  
This device may be used as a level converter for interfacing 3.3  
V to 5 V system.  
Input protection and output circuit ensure that 0 to 5.5 V can  
be applied to the input and output (Note) pins without regard to  
the supply voltage. These structure prevents device destruction  
due to mismatched supply and input/output voltages such as  
battery back up, hot board insertion, etc.  
TC74VHCT373AF  
TC74VHCT373AFT  
TC74VHCT373AFK  
Note:  
Output in off-state  
Features  
High speed: t = 7.7 ns (typ.) at V  
= 5 V  
pd  
CC  
Low power dissipation: I  
= 4 μA (max) at Ta = 25°C  
CC  
Compatible with TTL inputs:  
V
V
= 0.8 V (max)  
= 2.0 V (min)  
IL  
IH  
Power down protection is provided on all inputs and outputs.  
Balanced propagation delays: t t  
pLH  
pHL  
Low noise: V  
= 1.5 V (max)  
OLP  
Pin and function compatible with the 74 series  
(74AC/HC/F/ALS/LS etc.) 373 type.  
Weight  
SOP20-P-300-1.27A:  
0.22 g (typ.)  
TSSOP20-P-0044-0.65A: 0.08 g (typ.)  
VSSOP20-P-0030-0.50:  
0.03 g (typ.)  
1
2008-12-01  

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