TC74VHC367,368F/FN/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC367F,TC74VHC367FN,TC74VHC367FT,TC74VHC367FK
TC74VHC368F,TC74VHC368FN,TC74VHC368FT,TC74VHC368FK
Hex Bus Buffer
TC74VHC367F/FN/FT Non-Inverted, 3-State
Note: The JEDEC SOP (FN) is not available in
Outputs
Japan.
TC74VHC368F/FN/FT Inverted, 3-State
TC74VHC367F, TC74VHC368F
Outputs
The TC74VHC367 and 368 are advanced high speed CMOS
HEX BUS BUFFERs fabricated with silicon gate C2MOS
technology.
They achieve the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
TC74VHC367FN, TC74VHC368FN
They contain six buffers; four buffers are controlled by an
enable input ( G1 ), and the other two buffers are controlled by
another enable input (G2 ). The outputs of each buffer group are
enabled when G1 and/or G2 inputs are held low; if held high,
these outputs are in a high impedance state.
The TC74VHC367 is a non-inverting output type, while the
TC74VHC368 is an inverting output type.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
TC74VHC367FT, TC74VHC368FT
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
•
•
•
•
•
•
•
•
High speed: t = 3.8 ns (typ.) at V
= 5 V
pd
CC
Low power dissipation: I
= 4 μA (max) at Ta = 25°C
CC
High noise immunity: V
= V
= 28% V
(min)
NIH
NIL
CC
TC74VHC367FK, TC74VHC368FK
Power down protection is provided on all inputs.
∼
−
Balanced propagation delays: t
t
pHL
pLH
Wide operating voltage range: V
= 2 V to 5.5 V
CC (opr)
Low noise: V
= 0.8 V (max)
OLP
Pin and function compatible with 74ALS367/368
Weight
SOP16-P-300-1.27A
SOL16-P-150-1.27
: 0.18 g (typ.)
: 0.13 g (typ.)
TSSOP16-P-0044-0.65A : 0.06 g (typ.)
VSSOP16-P-0030-0.50
: 0.02 g (typ.)
1
2007-10-01