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TC74VHC367FN(F,M) PDF预览

TC74VHC367FN(F,M)

更新时间: 2024-11-09 13:14:31
品牌 Logo 应用领域
东芝 - TOSHIBA 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 269K
描述
IC,BUFFER/DRIVER,DUAL,2-BIT/4-BIT,AHC/VHC-CMOS,SOP,16PIN,PLASTIC

TC74VHC367FN(F,M) 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:SOP, SOP16,.25Reach Compliance Code:unknown
风险等级:5.84控制类型:ENABLE LOW
JESD-30 代码:R-PDSO-G16负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
位数:6功能数量:2
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:2/5.5 V认证状态:Not Qualified
子类别:Bus Driver/Transceivers表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

TC74VHC367FN(F,M) 数据手册

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TC74VHC367,368F/FN/FT/FK  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74VHC367F,TC74VHC367FN,TC74VHC367FT,TC74VHC367FK  
TC74VHC368F,TC74VHC368FN,TC74VHC368FT,TC74VHC368FK  
Hex Bus Buffer  
TC74VHC367F/FN/FT Non-Inverted, 3-State  
Note: The JEDEC SOP (FN) is not available in  
Outputs  
Japan.  
TC74VHC368F/FN/FT Inverted, 3-State  
TC74VHC367F, TC74VHC368F  
Outputs  
The TC74VHC367 and 368 are advanced high speed CMOS  
HEX BUS BUFFERs fabricated with silicon gate C2MOS  
technology.  
They achieve the high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low power  
dissipation.  
TC74VHC367FN, TC74VHC368FN  
They contain six buffers; four buffers are controlled by an  
enable input ( G1 ), and the other two buffers are controlled by  
another enable input (G2 ). The outputs of each buffer group are  
enabled when G1 and/or G2 inputs are held low; if held high,  
these outputs are in a high impedance state.  
The TC74VHC367 is a non-inverting output type, while the  
TC74VHC368 is an inverting output type.  
An input protection circuit ensures that 0 to 5.5 V can be  
applied to the input pins without regard to the supply voltage.  
This device can be used to interface 5 V to 3 V systems and two  
TC74VHC367FT, TC74VHC368FT  
supply systems such as battery back up. This circuit prevents  
device destruction due to mismatched supply and input voltages.  
Features  
High speed: t = 3.8 ns (typ.) at V  
= 5 V  
pd  
CC  
Low power dissipation: I  
= 4 μA (max) at Ta = 25°C  
CC  
High noise immunity: V  
= V  
= 28% V  
(min)  
NIH  
NIL  
CC  
TC74VHC367FK, TC74VHC368FK  
Power down protection is provided on all inputs.  
Balanced propagation delays: t  
t
pHL  
pLH  
Wide operating voltage range: V  
= 2 V to 5.5 V  
CC (opr)  
Low noise: V  
= 0.8 V (max)  
OLP  
Pin and function compatible with 74ALS367/368  
Weight  
SOP16-P-300-1.27A  
SOL16-P-150-1.27  
: 0.18 g (typ.)  
: 0.13 g (typ.)  
TSSOP16-P-0044-0.65A : 0.06 g (typ.)  
VSSOP16-P-0030-0.50  
: 0.02 g (typ.)  
1
2007-10-01  

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