TC74VHC138F(EL,F)

更新时间： 2024-09-28 13:14:31

品牌	Logo	应用领域
东芝 - TOSHIBA		解码器驱动器逻辑集成电路光电二极管
页数	文件大小	规格书
10页	260K
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TC74VHC138F/FN/FT/FK

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74VHC138F,TC74VHC138FN,TC74VHC138FT,TC74VHC138FK

3-to-8 Line Decoder

Note: xxxFN (JEDEC SOP) is not available in

The TC74VHC138 is an advanced high speed CMOS 3-to-8

DECODER fabricated with silicon gate C2MOS technology.

Japan.

It achieves the high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low power

dissipation.

When the device is enabled, 3 Binary Select inputs (A, B and

C) determine which one of the outputs ( Y0 - Y7 ) will go low.

When enable input G1 is held low or eitherG2A or G2B is held

high, decoding function is inhibited and all outputs go high.

G1, G2A , and G2B inputs are provided to ease cascade

connection and for use as an address decoder for memory

systems.

An input protection circuit ensures that 0 to 5.5 V can be

applied to the input pins without regard to the supply voltage.

This device can be used to interface 5 V to 3 V systems and two

supply systems such as battery back up. This circuit prevents

device destruction due to mismatched supply and input voltages.

TC74VHC138F

TC74VHC138FN

TC74VHC138FT

TC74VHC138FK

Features

•

High speed: t = 5.7 ns (typ.) at V

= 5 V

Low power dissipation: I

= 4 μA (max) at Ta = 25°C

High noise immunity: V

= V

= 28% V

NIH

NIL CC (min)

Power down protection is provided on all inputs.

∼

−

Balanced propagation delays: t

pHL

pLH

Wide operating voltage range: V

= 2 V to 5.5 V

CC (opr)

Pin and function compatible with 74ALS138

Weight

SOP16-P-300-1.27A

SOL16-P-150-1.27

: 0.18 g (typ.)

: 0.13 g (typ.)

TSSOP16-P-0044-0.65A : 0.06 g (typ.)

VSSOP16-P-0030-0.50

: 0.02 g (typ.)

2007-10-01

12 3 4 5 6 7...10

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