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TC74VCX16823FT PDF预览

TC74VCX16823FT

更新时间: 2024-09-14 04:49:35
品牌 Logo 应用领域
东芝 - TOSHIBA 总线驱动器总线收发器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 223K
描述
Low-Voltage 18-Bit D-Type Flip-Flop with 3.6-V Tolerant Inputs and Outputs

TC74VCX16823FT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:End Of Life零件包装代码:TSSOP
包装说明:6.10 MM, 0.50 MM PITCH, PLASTIC, TSSOP-56针数:56
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.7Is Samacsys:N
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G56
JESD-609代码:e4长度:14 mm
负载电容(CL):30 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:250000000 Hz最大I(ol):0.024 A
位数:9功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V传播延迟(tpd):8.8 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:GOLD
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:6.1 mm
Base Number Matches:1

TC74VCX16823FT 数据手册

 浏览型号TC74VCX16823FT的Datasheet PDF文件第2页浏览型号TC74VCX16823FT的Datasheet PDF文件第3页浏览型号TC74VCX16823FT的Datasheet PDF文件第4页浏览型号TC74VCX16823FT的Datasheet PDF文件第5页浏览型号TC74VCX16823FT的Datasheet PDF文件第6页浏览型号TC74VCX16823FT的Datasheet PDF文件第7页 
TC74VCX16823FT  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74VCX16823FT  
Low-Voltage 18-Bit D-Type Flip-Flop with 3.6-V Tolerant Inputs and Outputs  
The TC74VCX16823FT is a high-performance CMOS 18-bit  
D-type flip-flop. Designed for use in 1.8-V, 2.5-V or 3.3-V systems,  
it achieves high-speed operation while maintaining the CMOS  
low power dissipation.  
It is also designed with overvoltage tolerant inputs and outputs  
up to 3.6 V.  
The TC74VCX16823FT can be used as two 9-bit flip-flops or  
one 18-bit flip-flop. With the clock-enable (CKEN) input low, the  
D-type flip-flops enter data on the low-to-high transitions of the  
clock. Taking CKEN high disables the clock buffer, thus latching  
the outputs. Taking the clear (CLR) input low causes the Q  
Weight: 0.25 g (typ.)  
outputs to go low independently of the clock. When the OE input  
is high, the outputs are in a high-impedance state. This device is designed to be used with 3-state memory address  
drivers, etc.  
All inputs are equipped with protection circuits against static discharge.  
Features  
Low-voltage operation: V  
= 1.8 to 3.6 V  
CC  
High-speed operation: t = 3.5 ns (max) (V  
= 3.0 to 3.6 V)  
= 2.3 to 2.7 V)  
= 1.8 V)  
pd  
CC  
CC  
CC  
: t = 4.4 ns (max) (V  
pd  
: t = 8.8 ns (max) (V  
pd  
Output current: I /I  
= ±24 mA (min) (V  
= ±18 mA (min) (V  
= 3.0 V)  
OH OL  
CC  
CC  
: I /I  
OH OL  
= 2.3 V)  
: I /I  
OH OL  
= ±6 mA (min) (V  
= 1.8 V)  
CC  
Latch-up performance: 300 mA  
ESD performance:Machine model ≥ ±200 V  
Human body model ≥ ±2000 V  
Package: TSSOP  
3.6-V tolerant function and power-down protection provided on all inputs and outputs  
1
2007-10-19  

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