Datasheet > TC74HC4514AP_07

TC74HC4514AP_07

更新时间： 2024-09-23 05:04:11

品牌	Logo	应用领域
东芝 - TOSHIBA		锁存器
页数	文件大小	规格书
8页	326K
描述
4-to-16 Line Decoder/Latch

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中文翻译

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数据手册

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TC74HC4514AP_07 数据手册

TC74HC4514AP

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74HC4514AP

4-to-16 Line Decoder/Latch

The TC74HC4514A are high speed CMOS 4-LINE TO 16-LINE

DECODER WITH LATCHED INPUTs fabricated with silicon

gate C²MOS technology.

It achieves the high speed operation similar to equivalent

LSTTL while maintaining the CMOS low power dissipation.

The selected output is enabled by a low on the inhibit input

(INHIBIT). A binary code stored in the four input latches (A thru

D) is decided and provides a high level at the corresponding one

of sixteen outputs. When the INHIBIT is held low, all outputs are

kept low however, the latch function is available.

The data applied to the data inputs are transferred to the

outputs of latches when the strobe input is held high. When the

strobe input is taken low, the data is retained at the output of the latches.

Weight: 1.50 g (typ.)

All inputs are equipped with protection circuits against static discharge or transient excess voltage.

Features

•

High speed: t = 18 ns (typ.) at V

= 5 V

Low power dissipation: I

= 4 μA (max) at Ta = 25°C

High noise immunity: V

= V

= 28% V

(min)

NIH

NIL

Output drive capability: 10 LSTTL loads

Symmetrical output impedance: |I | = I

= 4 mA (min)

∼

−

Balanced propagation delays: t

pHL

pLH

Wide operating voltage range: V

(opr) = 2 to 6 V

Pin and function compatible with 4514B

Pin Assignment

2007-10-01

12 3 4 5 6 7 8

中文翻译

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