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TC74AC112P_07 PDF预览

TC74AC112P_07

更新时间: 2024-09-15 05:04:11
品牌 Logo 应用领域
东芝 - TOSHIBA 触发器
页数 文件大小 规格书
9页 313K
描述
CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip Flop with Preset and Clear

TC74AC112P_07 数据手册

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TC74AC112P/F/FN  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74AC112P,TC74AC112F,TC74AC112FN  
Dual J-K Flip Flop with Preset and Clear  
Note: xxxFN (JEDEC SOP) is not available in  
Japan.  
The TC74AC112 is an advanced high speed CMOS DUAL J-K  
FLIP FLOP fabricated with silicon gate and double-layer metal  
wiring C2MOS technology.  
TC74AC112P  
It achieves the high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low power  
dissipation.  
In accordance with the logic level given J and K input this  
device changes state on negative going transition of the clock  
pulse. CLEAR and PRESET are independent of the clock and  
accomplished by a low logic level on the corresponding input.  
All inputs are equipped with protection circuits against static  
TC74AC112F  
discharge or transient excess voltage.  
Features  
High speed: f  
= 170 MHz (typ.) at V  
= 5 V  
max  
CC  
Low power dissipation: I  
= 4 μA (max) at Ta = 25°C  
CC  
High noise immunity: V  
= V  
= 28% V  
(min)  
NIH  
NIL  
CC  
Symmetrical output impedance: |I | = I  
= 24 mA (min)  
OH  
OL  
Capability of driving 50 Ω  
TC74AC112FN  
transmission lines.  
t
pHL  
(opr) = 2 to 5.5 V  
Balanced propagation delays: t  
pLH  
Wide operating voltage range: V  
CC  
Pin and function compatible with 74F112  
Pin Assignment  
Weight  
DIP16-P-300-2.54A  
SOP16-P-300-1.27A  
SOL16-P-150-1.27  
: 1.00 g (typ.)  
: 0.18 g (typ.)  
: 0.13 g (typ.)  
1
2007-10-01  

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