Datasheet > TC74AC109F_12

TC74AC109F_12

更新时间： 2024-09-15 12:22:59

品牌	Logo	应用领域
东芝 - TOSHIBA		触发器
页数	文件大小	规格书
8页	267K
描述
Dual J-K Flip Flop with Preset and Clear

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数据手册

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TC74AC109F_12 数据手册

TC74AC109P/F

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74AC109P,TC74AC109F

Dual J-K Flip Flop with Preset and Clear

TC74AC109P

The TC74AC109 is an advanced high speed CMOS DUAL J- K

FLIP FLOP fabricated with silicon gate and double-layer metal

wiring C²MOS technology.

It achieves the high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low power

dissipation.

In accordance with the logic level given J and K input this

device changes state on positive going transition of the clock

pulse. CLEAR and PRESET are independent of the clock and

accomplished by a low logic level on the corresponding input.

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

TC74AC109F

Features

•

High speed: f

= 200 MHz (typ.) at V

= 5 V

max

Low power dissipation: I

= 4 μA (max) at Ta = 25°C

High noise immunity: V

= V

= 28% V

(min)

NIH

NIL

Symmetrical output impedance: |I | = I

= 24 mA (min)

Weight

DIP16-P-300-2.54A

SOP16-P-300-1.27A

Capability of driving 50 Ω

transmission lines.

: 1.00 g (typ.)

: 0.18 g (typ.)

∼

−

pHL

•

Balanced propagation delays: t

pLH

Wide operating voltage range: V

(opr) = 2 to 5.5 V

Pin and function compatible with 74F109

Pin Assignment

2012-02-29

12 3 4 5 6 7 8

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