Datasheet > TC55WDM518AFFN22

TC55WDM518AFFN22

更新时间： 2024-11-10 20:44:35

品牌	Logo	应用领域
东芝 - TOSHIBA		静态存储器内存集成电路
页数	文件大小	规格书
20页	476K
描述
IC 2M X 18 ZBT SRAM, 2.8 ns, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100, Static RAM

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TC55WDM518AFFN22 技术参数

生命周期：	Active	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.79
最长访问时间：	2.8 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	37748736 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	18
功能数量：	1	端子数量：	100
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	2MX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	1.7 mm	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

TC55WDM518AFFN22 数据手册

TC55WDM518AFFN22/20/16/15

TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

36M 2.5V Pipelined NtRAM^TM2M Word by 18Bit

SYNCHRONOUS NO-TURNAROUND STATIC RAM

DESCRIPTION

The TC55WDM518AFFN is a synchronous static random access memory (SRAM) organized as 2,097,152 words

by 18 bits. NtRAM^TM(no-turnaround SRAM) offers high bandwidth by eliminating dead cycles during the

transition from a read to a write and vice versa. All inputs except Output Enable OE and the Snooze pin ZZ are

synchronized with the rising edge of the CLK input. A Read operation is initiated by the ADV Address Advanced

Input signal ; the input from the address pins and all control pins except the OE and ZZ pins are loaded into the

internal registers on the rising edge of CLK in the cycle in which ADV is asserted. The output data is available two

clock cycles later. Write operations are internally self-timed and are initiated by the rising edge of CLK in the cycle

in which ADV is asserted. The input from the address pins and all control pins except the OE and ZZ pins are

loaded into the internal registers on the rising edge of CLK in the cycle in which ADV is asserted. Input data is

loaded in the third cycle after the cycle in which ADV is asserted. Byte Write Enables ( BW1 to BW2 ) allow from

one to four Byte Write operations to be performed. A 2-bit burst address counter and control logic are integrated

into this SRAM. The TC55WDM518AFFN uses a single power supply (2.5V) and is available in a 100-pin low-

profile plastic QFP (LQFP).

FEATURES

•

Organized as 2,097,152 words by 18 bits

No-turnaround operation with pipeline data output

2-bit burst address counter

•

Single 2.5V 5% power supply V_DDand V_DDQ

Available in 100-pin LQFP package (LQFP100-P-

1420-0.65B ; ,weight :

grams (typical))

(support for interleaved or linear burst sequences)

Synchronous self-timed Write

MHz

•

225

4.4

2.8

200

5.0

3.2

167

6.0

3.5

150

6.6

3.8

Clock Cycle Time

Clock Access Time

Operating Current

Byte Write control

t_KC

t_KQV

Snooze mode pin (ZZ) for power down

LVTTL-compatible interface

I_DDO1

TBD

PIN ASSIGNMENT (TOP VIEW)

PIN NAMES

CLK

Clock Input

Address Inputs

A0 to A20

99 97 95 93 91 89 87 85 83 81

100 98 96 94 92 90 88 86 84 82

A18

CE , CE2 , CE2 Chip Enable Inputs

Output Enable Input

Write Enable input

V^DDQ

V^SSQ

V^DDQ

V^SSQ

I/OP1

I/O8

I/O7

V^SSQ

V^DDQ

I/O6

I/O5

V^SS

BW1 to BW2 Byte Write Enable

I/O9

I/O10

V^SSQ

V^DDQ

I/O11

I/O12

V^DD

ADV

CKE

Address Advance Input

Clock Enable

Snooze Input

V^DD

I/O1 to I/O16

Data Inputs/Outputs

V^SS

I/O13

I/O14

V^DDQ

V^SSQ

I/O15

I/O16

I/OP2

I/O4

I/O3

V^DDQ

V^SSQ

I/O2

I/O1

I/OP1 to I/OP2 Parity Data Inputs/Outputs

MODE

Mode select Input

No Connection

Not Usable

V^SSQ

V^DDQ

V^SSQ

V^DDQ

Power Supply for Core

Power Supply for Output Buffer

Ground for Core

DDQ

32 34 36 38 40 42 44 46 48 50

31 33 35 37 39 41 43 45 47 49

Ground for Output Buffer

SSQ

Note :

NtRAM

and No-Turnaround Random Access

Memory are trademarks of Samsung Electronics Co., Ltd..

2003-01-08 1/20

12 3 4 5 6 7...20

中文翻译

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与TC55WDM518AFFN22相关器件

型号	品牌	获取价格	描述	数据表
TC55WDM536AFFN15	TOSHIBA	获取价格	IC 1M X 36 ZBT SRAM, 3.8 ns, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100, Static
TC55WDM536AFFN20	TOSHIBA	获取价格	IC 1M X 36 ZBT SRAM, 3.2 ns, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100, Static
TC55WDM536AFFN22	TOSHIBA	获取价格	IC 1M X 36 ZBT SRAM, 2.8 ns, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100, Static
TC55WK818FF-267	TOSHIBA	获取价格	IC 512K X 18 CACHE SRAM, PQFP100, 14 X 20 MM, 1.60 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP
TC55WK818FF-333	TOSHIBA	获取价格	IC 512K X 18 CACHE SRAM, PQFP100, 14 X 20 MM, 1.60 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP
TC55WK836FF-267	TOSHIBA	获取价格	IC 256K X 36 CACHE SRAM, 0.4 ns, PQFP100, 14 X 20 MM, 1.60 MM HEIGHT, 0.65 MM PITCH, PLAST
TC55WK836FF-333	TOSHIBA	获取价格	IC 256K X 36 CACHE SRAM, 0.4 ns, PQFP100, 14 X 20 MM, 1.60 MM HEIGHT, 0.65 MM PITCH, PLAST
TC55WK837XB-300	TOSHIBA	获取价格	IC 256K X 36 CACHE SRAM, 0.4 ns, PBGA153, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-153, Sta
TC55WK837XB-333	TOSHIBA	获取价格	IC 256K X 36 CACHE SRAM, 0.4 ns, PBGA153, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-153, Sta
TC55WL1618FF-75	TOSHIBA	获取价格	IC 1M X 18 STANDARD SRAM, 10 ns, PQFP100, 14 X 20 MM, 1.60 MM HEIGHT, 0.65 MM PITCH, PLAST

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