T80C5111
Low-pin-count 8-bit microcontroller with A/D converter
1. Description
The T80C5111 is a high performance ROM/OTP version the same CPU power at a divided by two oscillator
of the 80C51 8-bit microcontroller in Low Pin Count frequency. The prescaler allows to decrease CPU and
package.
peripherals clock frequency.
The T80C5111 retains all the features of the standard The fully static design of the T80C5111 allows to reduce
80C51 with 4 Kbytes ROM/OTP program memory, 256 system power consumption by bringing the clock
bytes of internal RAM, a 8-source , 4-level interrupt frequency down to any value, even DC, without loss of
system, an on-chip oscillator and two timer/counters.
data.
The T80C5111 is dedicated for analog interfacing The T80C5111 has 3 software-selectable modes of
applications. For this, it has an 10-bit, 8 channels A/D reduced activity for further reduction in power
converter and a five channels Programmable Counter consumption. In the idle mode the CPU is frozen while
Array.
the peripherals are still operating. In the quiet mode, the
A/D converter only is operating. In the power-down
mode the RAM is saved and all other functions are
inoperative. Two oscillators source, crystal and RC,
provide a versatile power management.
In addition, the T80C5111 has a Hardware Watchdog
Timer with its own low power oscillator, a versatile
serial
channel
that
facilitates
multiprocessor
communication (EUART) with an independent baud rate
generator, a SPI serial bus controller and a X2 speed The T80C5111 is proposed in low pin count packages.
improvement mechanism. The X2 feature allows to keep Port 0 and Port 2 (address / data busses) are not available .
2. Features
•
80C51 Compatible
•
Dual system clock
•
•
•
Three I/O ports
•
Crystal or ceramic oscillator with hardware set
up (32 KHz or 33/40 MHz)
Two 16-bit timer/counters
256 bytes RAM
•
•
•
Internal RC oscillator (12 MHz)
Programmable prescaler
•
•
4 Kbytes ROM/OTP program memory with 64 bytes
encryption array and 3 security levels.
Active oscillator during reset defined by hardware
set up
High-Speed Architecture
•
Timer 0 subclock mode for Real Time Clock.
•
•
•
33MHz @ 5V (66 MHz equivalent)
20MHz @ 3V (40 MHz equivalent)
•
•
Programmable counter array with High speed output,
Compare / Capture, Pulse Width Modulation and
Watchdog timer capabilities
X2 Speed Improvement capability (6 clocks/
machine cycle)
Interrupt Structure with:
•
•
•
10-bit, 8 channels A/D converter
•
•
8 Interrupt sources,
Voltage reference for A/D & external analog
4 interrupt priority levels
Hardware Watchdog Timer with integrated low
power oscillator (20µA).
•
Power Control modes:
•
•
•
Idle mode
•
•
Programmable I/O mode: standard C51, input only,
push-pull, open drain.
Power-down mode
Power-off Flag, Power fail detect, Power on Reset
Asynchronous port reset, Power On Reset, Power
fail Detect
•
•
Power supply: 2.7 to 5.5V
o
Temperature ranges: Commercial (0 to 70 C) and
Industrial (-40 to 85 C)
•
•
Full duplex Enhanced UART with baud rate generator
SPI, master/slave mode
o
Rev. B - November 10, 2000
1
Preliminary