T83C5101XXX-TIRCV PDF预览

T83C5101XXX-TIRCV

更新时间: 2025-01-18 03:29:23
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
58页 743K
描述
8-bit Low Pin Count Microcontrollers

T83C5101XXX-TIRCV 数据手册

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Features  
80C51 Code Compatible  
– 8051 Instruction Compatible  
– 16 I/O + 2 Outputs in 24 Pin Packages  
16 I/O + 6 Outputs in 28 Pin Packages  
– Three 16-bit Timer/Counters  
– 256 Bytes Scratchpad RAM  
Program Memory  
8 KB ROM T83C5102  
16 KB ROM T83C5101  
16 KB EPROM/OTP T87C5101  
High-speed Architecture  
8-bit Low Pin  
Count  
Microcontrollers  
40 MHz from 2.7 to 5.5V, Commercial or Industrial Temperature Range:  
40 MHz with a 40 MHz Crystal In Std. Mode  
40 MHz with a 20 MHz Crystal In X2 Mode  
66 MHz from 4.5 to 5.5V, Commercial Temperature Range  
40 MHz with a 40 MHz Crystal in Std. Mode  
66 MHz with a 33 MHz Crystal in X2 Mode  
Dual Data Pointer  
On-chip eXpanded RAM (XRAM) (256 bytes)  
Programmable Clock Out and Up/Down Timer/Counter 2  
Asynchronous Port Reset  
T83C5101  
T87C5101  
T83C5102  
Interrupt Structure with  
6 Interrupt Sources,  
4-Level Priority Interrupt System  
Full-duplex Enhanced UART  
Framing Error Detection  
Automatic Address Recognition  
Low EMI (no ALE)  
Power Control Modes  
Idle Mode  
Power-down Mode  
Packages: SO24, DIL24, SSOP24, SO28  
Description  
The T8xC5101/02 family is a high performance CMOS ROM, OTP, EPROM derivative  
of the 80C51 CMOS single chip 8-bit microcontroller.  
The T8xC5101/02 family is a low pin count device where only Port 1, port 3 and 2/6  
bits of a new port 4 are outputted. This prevents any external access, like external pro-  
gram memory access (fetch, MOVC) or external data memory (MOVX). The  
T8xC5101/02 family retains all features of the 80C51 with extended capacity 8 KB  
ROM (5102), 16 KB ROM (5101)/16 KB EPROM/OTP (5101), 256 bytes of internal  
RAM, a 6-source, 4-level interrupt system, an on-chip oscillator and three  
timer/counters.  
In addition, the T8xC5101/02 family has an XRAM of 256 bytes, the X2 feature, a  
more versatile serial channel that facilitates multiprocessor communication (EUART),  
a dual data pointer and an improved timer 2. The fully static design of the  
T8xC5101/02 family allows to reduce system power consumption by bringing the  
clock frequency down to any value, even DC, without loss of data.  
The T8xC5101/02 family has 2 software-selectable modes of reduced activity for fur-  
ther reduction in power consumption. In idle mode the CPU is frozen while the timers,  
the serial port and the interrupt system are still operating. In power-down mode the  
RAM is saved and all other functions are inoperative.  
Rev. 4233G–8051–03/03  
1

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