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T80C5112_00

更新时间： 2024-11-07 03:29:23
品牌 Logo 应用领域
爱特美尔 - ATMEL 转换器微控制器
页数 文件大小 规格书
97页 764K
描述
8-bit Microcontroller with A/D converter

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T80C5112_00 数据手册

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T80C5112  
8-bit Microcontroller with A/D converter  
1. Description  
The T80C5112 is a high performance ROM/OTP version improvement mechanism. The X2 feature allows to keep  
of the 80C51 8-bit microcontroller.  
the same CPU power at a divided by two oscillator  
frequency.  
The T80C5112 retains all the features of the standard  
80C51 with 8 Kbytes ROM/OTP program memory, 256 The fully static design of the T80C5112 allows to reduce  
bytes of internal RAM, a 8-source , 4-level interrupt system power consumption by bringing the clock  
system, an on-chip oscillator and two timer/counters.  
frequency down to any value, even DC, without loss of  
data.  
The T80C5112 is dedicated for analog interfacing  
applications. For this, it has an 10-bit, 8 channels A/D The T80C5112 has 3 software-selectable modes of  
converter and a five channels Programmable Counter reduced activity for further reduction in power  
Array.  
consumption. In the idle mode the CPU is frozen while  
the peripherals are still operating. In the quiet mode, the  
A/D converter only is operating. In the power-down  
mode the RAM is saved and all other functions are  
inoperative. Two oscillators source, crystal and RC,  
provide a versatile power management.  
In addition, the T80C5112 has a Hardware Watchdog  
Timer with its own low power oscillator, a versatile  
serial  
communication (EUART) with an independent baud rate  
generator, a SPI serial bus controller and a X2 speed  
channel  
that  
facilitates  
multiprocessor  
The T80C5112 is proposed in 48/52 pin count packages  
with Port 0 and Port 2 (address / data busses).  
2. Features  
·
80C51 Compatible  
·
Crystal or ceramic oscillator with hardware set  
up (32 KHz or 33/40 MHz)  
·
·
·
Five I/O ports  
·
·
·
Internal RC oscillator (12 MHz)  
Programmable prescaler  
Two 16-bit timer/counters  
256 bytes RAM  
Active oscillator during reset defined by hardware  
set up  
·
·
8Kbytes ROM/OTP program memory with 64 bytes  
encryption array and 3 security levels.  
·
Timer 0 subclock mode for Real Time Clock.  
High-Speed Architecture  
·
·
Programmable counter array with High speed output,  
Compare / Capture, Pulse Width Modulation and  
Watchdog timer capabilities  
·
·
·
33MHz @ 5V (66 MHz equivalent)  
20MHz @ 3V (40 MHz equivalent)  
X2 Speed Improvement capability (6 clocks/  
machine cycle)  
Interrupt Structure with:  
·
·
8 Interrupt sources,  
·
·
10-bit, 8 channels A/D converter  
4 interrupt priority levels  
Hardware Watchdog Timer with integrated low  
power oscillator (20mA) and Reset-Out  
·
Power Control modes:  
·
·
·
Idle mode  
·
Programmable I/O mode: standard C51, input only,  
push-pull, open drain.  
Power-down mode  
Power-off Flag, Power fail detect, Power on Reset  
·
·
·
·
Asynchronous port reset, Power On Reset  
Full duplex Enhanced UART with baud rate generator  
SPI, master/slave mode  
·
·
Power supply: 2.7 to 5.5V  
Temperature ranges: Commercial (0 to 70C) and  
Industrial (-40 to 85 C), optionnal extented  
Dual system clock  
·
Package:LQFP48 (body 7*7*1.4mm), PLCC52  
Rev. B - November 10, 2000  
1
Preliminary  
1234567...97

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