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SYS8V2000FKX-70 PDF预览

SYS8V2000FKX-70

更新时间: 2024-11-11 16:57:59
品牌 Logo 应用领域
MOSAIC 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
7页 112K
描述
SRAM Module, 2MX8, 70ns, CMOS, PDIP36, PLASTIC, DIP-36

SYS8V2000FKX-70 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:,针数:36
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:70 nsJESD-30 代码:R-PDIP-T36
内存密度:16777216 bit内存集成电路类型:SRAM MODULE
内存宽度:8功能数量:1
端子数量:36字数:2097152 words
字数代码:2000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2MX8封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL认证状态:Not Qualified
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子位置:DUAL
Base Number Matches:1

SYS8V2000FKX-70 数据手册

 浏览型号SYS8V2000FKX-70的Datasheet PDF文件第2页浏览型号SYS8V2000FKX-70的Datasheet PDF文件第3页浏览型号SYS8V2000FKX-70的Datasheet PDF文件第4页浏览型号SYS8V2000FKX-70的Datasheet PDF文件第5页浏览型号SYS8V2000FKX-70的Datasheet PDF文件第6页浏览型号SYS8V2000FKX-70的Datasheet PDF文件第7页 
2M x 8 SRAM MODULE  
SYS8V2000FKX - 70/85/10/12  
11403 West Bernado Court, Suite 100, San Diego, CA 92127.  
Tel No: (001) 858 674 2233, Fax No: (001) 858 674 2230  
Issue 1.0 : February 2000  
Description  
Features  
Access Times of 70/85/100/120 ns.  
36 Pin JEDEC standard Dual-In-Line package.  
3.3 Volt Supply ± 10%.  
The SYS8V2000FKX is a plastic 3.3V 16Mbit Static  
RAM Module housed in a JEDEC standard 36 pin  
Dual In-Line package organised as 2Mx8.  
The module utilises 512Kx8 SRAM's housed in  
TSOP II packages, and uses double sided surface  
mount techniques, buried decoder and dual board  
construction to achieve a very high density module,  
emulating the 16Mbit monolithic pinout.  
Center Power and Ground Pinout.  
Low Power Dissipation:  
Operating (max)  
Standby (CMOS)  
266mW (max).  
11.4mW (max).  
Low Voltage VCC Data Retention.  
Equal Access and Cycle Times.  
Directly TTL Compatible.  
Access times of 70 to 120 ns are available. The OE  
pin allows faster access times than address access  
during a read cycle.  
On-board Supply Decoupling Capacitors.  
Block Diagram  
Pin Definition  
A0 - A18  
A0  
A1  
A2  
A3  
A4  
1
2
3
4
5
6
7
8
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
A20  
A19  
A18  
A17  
A16  
OE  
D7  
D6  
GND  
Vcc  
D5  
D0 - D7  
WE  
OE  
512K X 8  
SRAM  
512K X 8  
SRAM  
512K X 8  
SRAM  
512K X 8  
SRAM  
CS  
D0  
D1  
Vcc  
GND  
D2  
D3  
WE  
A5  
CS  
CS  
CS  
CS  
TOP VIEW  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
D4  
CS  
A19  
A20  
DECODER  
A15  
A14  
A13  
A12  
A11  
A10  
A6  
A7  
A8  
A9  
Pin Functions  
Address Inputs  
A0 - A20  
D0 - D7  
CS  
Data Input/Output  
Chip Select  
Package Details  
Write Enable  
Output Enable  
Power (+5V)  
Ground  
WE  
Plastic 36 Pin 0.6" Dual-In-Line low  
profile Package.(DIP)  
OE  
VCC  
GND  

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