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SYS88000RKXLI-12 PDF预览

SYS88000RKXLI-12

更新时间: 2024-11-11 03:14:15
品牌 Logo 应用领域
MOSAIC 存储内存集成电路静态存储器
页数 文件大小 规格书
7页 84K
描述
8M x 8 SRAM MODULE

SYS88000RKXLI-12 技术参数

生命周期:Obsolete零件包装代码:SIP
包装说明:,针数:38
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.37
Is Samacsys:N最长访问时间:120 ns
JESD-30 代码:R-PSMA-T38内存密度:67108864 bit
内存集成电路类型:SRAM MODULE内存宽度:8
功能数量:1端子数量:38
字数:8388608 words字数代码:8000000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8MX8
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY并行/串行:PARALLEL
认证状态:Not Qualified最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子位置:SINGLEBase Number Matches:1

SYS88000RKXLI-12 数据手册

 浏览型号SYS88000RKXLI-12的Datasheet PDF文件第2页浏览型号SYS88000RKXLI-12的Datasheet PDF文件第3页浏览型号SYS88000RKXLI-12的Datasheet PDF文件第4页浏览型号SYS88000RKXLI-12的Datasheet PDF文件第5页浏览型号SYS88000RKXLI-12的Datasheet PDF文件第6页浏览型号SYS88000RKXLI-12的Datasheet PDF文件第7页 
8M x 8 SRAM MODULE  
SYS88000RKX - 70/85/10/12  
Issue 1.5: April 2001  
Description  
Features  
The SYS88000RKX is a plastic 64Mbit Static RAM  
Module housed in a standard 38 pin Single In-Line  
package organised as 8M x 8 with access times of  
85,100, or 120 ns.  
Access Times of 85/100/120 ns.  
Low Power Disapation:  
Operating  
Standby  
935 mW (Max.)  
11 mW (Max.)  
-L Version  
Themoduleisconstructedusingsixteen512Kx8SRAMs  
in TSOPII packages mounted onto both sides of an FR4  
epoxy substrate. This offers an extremely high PCB  
packing density.  
5 Volt Supply ± 10%.  
Completely Static Operation.  
Equal Access and Cycle Times.  
Low Voltage VCC Data Retention.  
On-board Decoding & Capacitors.  
38 Pin Single-In-Line package.  
Upgrade from SYS84000RKX (32Mbit).  
Thedeviceisofferedinstandardandlowpowerversions,  
with the -L module having a low voltage data retention  
modeforbatterybackedapplications.Onboardbuffering  
is provided to reduce output capacitance.  
Note: CS and OE on the module, should be used  
with care to avoid on and off board bus contention.  
Block Diagram  
Pin Definition  
A22  
A20  
Vcc  
WE  
D2  
1
2
3
4
5
D3  
6
D0  
7
A1  
8
A2  
A3  
A4  
GND  
D5  
A10  
A11  
A5  
A13  
A14  
A19  
CS  
A15  
A16  
A12  
A18  
A6  
D1  
GND  
A0  
A7  
9
OE  
WE  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
A0 - A18  
512K X 8  
SRAM  
T/R  
A19  
A20  
A21  
A22  
BI-DIRECTIONAL  
DRIVERS  
D0 - D7  
4 TO 16  
DECODER  
A0~7  
74FCT245  
OE  
D0 - D7  
B0~7  
512K X 8  
SRAM  
CS  
A8  
A9  
D7  
D4  
D6  
A17  
Vcc  
OE  
A21  
Pin Functions  
Address Inputs  
A0 ~ A22  
D0 ~ D7  
CS  
Data Input/Output  
Chip Select  
Package Details  
Plastic 38 pin Single-In-Line (SIP)  
Write Enable  
Output Enable  
No Connect  
Power (+5V)  
Ground  
WE  
OE  
NC  
VCC  
GND  

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