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SYS8512FKL-35 PDF预览

SYS8512FKL-35

更新时间: 2024-11-11 15:53:19
品牌 Logo 应用领域
MOSAIC 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
7页 108K
描述
SRAM Module, 512KX8, 35ns, CMOS, PDIP32, PLASTIC, DIP-32

SYS8512FKL-35 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:,针数:32
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.17
最长访问时间:35 nsJESD-30 代码:R-PDIP-T32
内存密度:4194304 bit内存集成电路类型:SRAM MODULE
内存宽度:8功能数量:1
端子数量:32字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX8封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL认证状态:Not Qualified
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子位置:DUAL
Base Number Matches:1

SYS8512FKL-35 数据手册

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Block Diagram  
                                                                                                                   
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512K x 8 SRAM MODULE  
SYS8512FK-20/25/35/45  
11403 West Bernado Court, Suite 100, San Diego, CA 92127.  
Tel No: (619) 674 2233, Fax No: (619) 674 2230  
Issue 5.0 : November 1999  
Description  
Features  
Access Times of 20/25/35/45 ns.  
The SYS8512FK is plastic 4M Static RAM Module  
housed in a standard 32 pin Dual-In-Line package  
organised as 512K x 8. The module utilises fast  
256Kx4 SRAMs housed in SOJ packages, and  
uses double sided surface mount techniques to  
achieve a very high density module.  
32 Pin 0.6" Dual-In-Line package with  
JEDEC compatible pinout.  
5 Volt Supply ± 10%.  
Low Power Dissipation:  
Average (min cycle)  
Standby -L (CMOS)  
2.42W (maximum).  
44mW (maximum).  
The module has Chip Select, Write Enable and  
Output Enable control inputs; the Output Enable  
pinallowsfasteraccesstimesthanaddressaccess  
during a Read Cycle.  
Completely Static Operation.  
Equal Access and Cycle Times.  
All Inputs and Outputs Directly TTL Compatible  
On-board Supply Decoupling Capacitors.  
A0 - A17  
D0 - D7  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A18  
A16  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
D0  
D1  
D2  
VCC  
A15  
A17  
WE  
A13  
A8  
WE  
OE  
256K X 4  
SRAM  
256K X 4  
SRAM  
256K X 4  
SRAM  
256K X 4  
SRAM  
A9  
A11  
OE  
A10  
CS  
D7  
D6  
D5  
D4  
D3  
CS  
CS  
CS  
CS  
9
10  
11  
12  
13  
14  
15  
16  
CS  
DECODER  
A18  
Pin Functions  
GND  
Address Inputs  
Data Input/Output  
Chip Select  
A0 - A18  
D0 - D7  
CS  
Package Details  
Write Enable  
Output Enable  
Power (+5V)  
Ground  
WE  
OE  
Plastic 32 pin 0.6" Jedec DIP  
VCC  
GND  

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