Datasheet > SY604JZ

SY604JZ

更新时间： 2024-11-06 22:58:07

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
8页	84K
描述
IC DELAY LINE 255TAP PROG 28PLCC

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中文翻译

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数据手册

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SY604JZ 数据手册

125MHz TRIGGER

PROGRAMMABLETIMING

EDGE VERNIER

SY604

FINAL

DESCRIPTION

FEATURES

■ True 125MHz retrigger rate

Micrel-Synergy'sSY604isanECL-compatibletimingvernier

(delay generator) whose time delay is programmed via an 8-

bit code which is loaded concurrently with the circuit trigger.

The SY604 is fabricated in Micrel-Synergy's proprietary

ASSET™ bipolar process.

This device can be retriggered at speeds up to 125MHz,

with a delay span as short as 4ns. At minimum span, the

resolution is 4ns/255 = 15.7ps per step. The delay span is

externally adjustable up to 40ns. The SY604 employs

differential TRIGGER inputs, and produces a differential

OUTPUT pulse; all other control signals are single-ended

ECL. Edge delay is specified by an 8-bit input which is loaded

into the device with the TRIGGER. The output pulse width will

typically be 3.5ns.

■ Pin-compatible with Bt604

■ 15ps delay resolution

■ Less than ± 1 LSB timing accuracy

■ Differential TRIGGER inputs

■ Delay spans from 4 to 40ns

■ Compatible with 10KH ECL logic

■ Lower power dissipation 350mW typical

■ Available in 28-pin plastic (PLCC) or metal (MLCC)

J-lead package

TheSY604iscommonlyusedinAutomaticTestEquipment

to provide precise timing edge placement; it is also found in

many instrumentation and communications applications.

Micrel-Synergy's circuit design techniques coupled with

ASSET™technologyresultinnotonlyultra-fastperformance,

but allow device operation at lower power dissipation than

competing technologies. Outstanding reliability is achieved in

volume production.

BLOCK DIAGRAM

I/V

D0 - D7

DAC

LATCH

PIN CONFIGURATION

–

PULSE

GEN

OUT

LINEAR

RAMP

GENERATOR

0 = STOP

1 = RUN

25 24 23 22 21 20 19

TRIG

COMP

TOP VIEW

PLCC

J28-1

COMP

VBB

IEXT

10 11

Rev.: E

Amendment: /0

Issue Date: May, 1998

12 3 4 5 6 7 8

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