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SY10EL52 PDF预览

SY10EL52

更新时间: 2024-11-01 22:59:23
品牌 Logo 应用领域
麦瑞 - MICREL 触发器时钟
页数 文件大小 规格书
4页 52K
描述
DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP

SY10EL52 数据手册

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DIFFERENTIAL DATA AND  
CLOCK D FLIP-FLOP  
SY10EL52  
SY100EL52  
FEATURES  
DESCRIPTION  
365ps propagation delay  
The SY10/100EL52 are differential data, differential  
clock D flip-flops. These devices are functionally  
equivalent to the E452 devices, with higher performance  
capabilities. With propagation delays and output transition  
times significantly faster than the E452, the EL52 is ideally  
suited for those applications which require the ultimate  
in AC performance.  
2.0GHz toggle frequency  
Internal 75Kinput pull-down resistors  
Available in 8-pin SOIC package  
Data enters the master portion of the flip-flop when  
the clock is LOW and is transferred to the slave, and  
thus the outputs, upon a positive transition of the clock.  
The differential clock inputs also allow the EL52 to be  
used as a negative edge triggered device.  
PIN CONFIGURATION/BLOCK DIAGRAM  
8
7
D
D
1
2
VCC  
Q
The EL52 employs input clamping circuitry so that,  
under open input conditions (pulled down to VEE), the  
outputs of the device will remain stable.  
D
Flip-Flop  
CLK  
CLK  
3
4
6
5
Q
VEE  
SOIC  
TOP VIEW  
(1)  
PIN NAMES  
TRUTH TABLE  
Pin  
D
Function  
D
L
CLK  
Z
Q
L
Data Input  
Clock Input  
Data Output  
CLK  
Q
H
Z
H
NOTE:  
1. Z = LOW-to-HIGH transition.  
Rev.: F  
Amendment:/0  
Issue Date: August, 1998  
1

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