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SY10EL51ZCTR PDF预览

SY10EL51ZCTR

更新时间: 2024-11-01 22:17:15
品牌 Logo 应用领域
麦瑞 - MICREL 触发器锁存器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
4页 53K
描述
DIFFERENTIAL CLOCK D FLIP-FLOP

SY10EL51ZCTR 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SOP, SOP8,.25Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.12
Is Samacsys:N其他特性:WITH DIFFERENTIAL CLOCK
系列:10ELJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.93 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:2200000000 Hz
湿度敏感等级:1位数:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):240电源:-5.2 V
最大电源电流(ICC):29 mAProp。Delay @ Nom-Sup:0.62 ns
传播延迟(tpd):0.565 ns认证状态:Not Qualified
座面最大高度:1.73 mm子类别:FF/Latches
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:3.94 mm
最小 fmax:2200 MHzBase Number Matches:1

SY10EL51ZCTR 数据手册

 浏览型号SY10EL51ZCTR的Datasheet PDF文件第2页浏览型号SY10EL51ZCTR的Datasheet PDF文件第3页浏览型号SY10EL51ZCTR的Datasheet PDF文件第4页 
DIFFERENTIAL  
CLOCK D FLIP-FLOP  
SY10EL51  
SY100EL51  
DESCRIPTION  
FEATURES  
475ps propagation delay  
The SY10/100EL51 are differential clock D flip-flops  
with reset. These devices are functionally similar to the  
E151 devices, with higher performance capabilities. With  
propagation delays and output transition times  
significantly faster than the E151, the EL51 is ideally  
suited for those applications which require the ultimate  
in AC performance.  
2.8GHz toggle frequency  
Internal 75Kinput pull-down resistors  
Available in 8-pin SOIC package  
The reset input is an asynchronous, level triggered  
signal. Data enters the master portion of the flip-flop  
when the clock is LOW and is transferred to the slave,  
and thus the outputs, upon a positive transition of the  
clock. The differential clock inputs of the EL51 allow the  
device to be used as a negative edge triggered flip-flop.  
The differential input employs clamp circuitry to  
maintain stability under open input (pulled down to VEE)  
conditions.  
PIN CONFIGURATION/BLOCK DIAGRAM  
8
7
R
D
1
2
VCC  
R
D
Q
Q
Flip-Flop  
6
5
CLK  
CLK  
3
4
V
EE  
SOIC  
TOP VIEW  
(1)  
PIN NAMES  
TRUTH TABLE  
Pin  
R
Function  
D
L
R
L
CLK  
Z
Q
L
Reset Input  
D
Data Input  
Clock Input  
Data Output  
H
X
L
Z
H
L
CLK  
Q
H
X
NOTE:  
1. Z = LOW-to-HIGH transition.  
Rev.: E  
Amendment:/0  
Issue Date: August, 1998  
1

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