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SXT6251 PDF预览

SXT6251

更新时间: 2024-11-16 21:03:15
品牌 Logo 应用领域
英特尔 - INTEL ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
68页 455K
描述
Support Circuit, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208

SXT6251 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:FQFP,针数:208
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.44JESD-30 代码:S-PQFP-G208
长度:28 mm功能数量:1
端子数量:208最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:FQFP封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH认证状态:Not Qualified
座面最大高度:4.1 mm标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:28 mm
Base Number Matches:1

SXT6251 数据手册

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DATA SHEET  
MAY 1998  
Revision 1.1  
SXT6251  
21 E1 SDH Mapper  
General Description  
Features  
The SXT6251 21E1 Mapper performs asynchronous map-  
ping and demapping of 21 E1 PDH signals into SDH. The  
PDH side interfaces with E1 LIUs and framers via NRZ  
Clock & Data, while the SDH side uses a standard Telecom  
bus interface. Further processing by the companion  
SXT6051 Overhead Terminator chip creates the final  
STM-0 or STM-1 signal. One mapper provides complete  
processing of 21 E1s in STM-0, while three mappers can  
process 63 E1s in STM-1.  
• Maps and Demaps 21 E1 signals between PDH and  
SDH networks via VC-12 asynchronous mapping.  
• Multiplexes the 21 VC-12 signals into seven inter-  
leaved TUG-2 structures for STM-0 or a TUG-3  
structure for STM-1 applications.  
• Configurable as a flexible Add/Drop Multiplexer for  
up to 21 E1 tributaries, with each E1 I/O port assign-  
able to any TU time slot within an AU-3 or TUG-3.  
• Performs VC-12 path overhead processing for all 21  
VC-12s, including V5, J2 Path Trace, and K4  
Enhanced RDI.  
The SXT6251 is compliant with the latest releases of ITU-  
T G.703 and G.707. It provides all the alarm and control  
features to easily implement the multiplexer specified in  
ITU-T G.783.  
• Records TU pointer alarms (TU-AIS, TU-LOP), BIP-  
2 and REI error counts, TIM and PLM alarms, and all  
other V5 POH alarms for all 21 tributaries.  
• NRZ Data and Clock interface for E1 tributary access.  
Applications  
• Microprocessor/SEMF interface to set Signal Label,  
J2 Path Trace, access alarms and counters  
• 21 or 63 E1 Terminal or ADM SDH Multiplexer  
• Digital Cross Connect System  
• Low power CMOS technology with 3.3V core and 5V  
I/O, available in PQFP-208 package.  
• Digital Loop Carrier Systems (NGDLC)  
• Microwave Radio Systems  
• IEEE 1149.1 (JTAG) support.  
SXT6251  
System Block Diagram  
SETS  
SXT 6251  
21 Channel  
M apper  
VC-12  
4
Telecom Bus Tim ing  
TX  
6.48M /19.44M C lock  
Fixed  
Pointer  
Generator  
Telecom  
Bus  
Interface  
21  
21  
Path  
E1 Clock  
Telecom Bus Data  
Term ination  
FIFO,  
S/P  
E1 Data  
E1 Line  
Interface  
units  
SXT 6051  
Overhead  
Terminator  
M icrocontroller Interface (Intel/M otorola selectable)  
21  
21  
E1 Clock  
E1 Data  
Telecom Bus Data  
6.48M /19.44M C lock  
Telecom Bus Tim ing  
FIFO, P/S,  
Desynchronizer  
VC-12  
Path  
Term ination  
Telecom  
Bus  
Interface  
Pointer  
Interpreter  
4
RX  

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