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SXT6051

更新时间： 2024-11-16 19:50:11
品牌 Logo 应用领域
LevelOne ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
144页 895K
描述
Terminator, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208

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SXT6051 数据手册

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DATA SHEET  
MAY 1998  
Revision 1.1  
SXT6051  
STM-1/0 SDH Overhead Terminator  
General Description  
Features  
The SXT6051 Overhead Terminator implements the  
Regenerator Section Termination, Multiplexer Section  
Termination and Higher Order Path Termination in STM-0  
(51Mb/s) and STM-1 (155mB/s) multiplexers. It provides  
micro-controller access for performance monitoring, alarm  
detection and configuration for transmit and receive paths.  
When used with the SXT6251 (21E1 Mapper), a complete  
solution for a 21 E1 or a 63 E1 Multiplexer is created.  
• Performs Regenerator Section, Multiplexer Section,  
and Higher Order Path Overhead Processing for  
STM-1 and STM-0 signals.  
• Byte parallel interface for STM-1 or STM-0, with  
byte alignment performed internally. Serial NRZ or  
B3ZS interface option for STM-0.  
• Demultiplexes STM-0/STM-1 signals to Telecom Bus  
output with optional pointer processor re-timing.  
• Multiplexes Telecom Bus data into STM-0 or STM-1  
signals with pointer processing.  
The SXT6051 is compliant with the latest releases of ITU-  
T G.703 and G.707. It provides all the alarm and control  
features to easily implement the multiplexer described in  
ITU-T G.783.  
• Compatible with 1+1 protected ITU architecture.  
• Records all RSOH, MSOH, and HPOH alarms. One  
second counters for B1, B2, B3, M1 REI and G1 REI.  
• Full J0/J1 trace identifier processing  
Applications  
• Serial access to STM-1 user-defined, media-depen-  
dent and national bytes.  
• Dedicated pins for serial access or pass-through fea-  
ture for E1, E2, F1, F2, F3, D1-D3 & D4-D12 bytes.  
• SDH Terminal Mux/ADM for microwave radio  
• ADM fiber ring Mux  
• Low power CMOS technology with 3.3V core and 5V  
I/O in PQFP-208 package.  
• Digital Loop Carrier (NGDLC) Systems  
• Digital Cross-Connect System  
• IEEE 1149.1 Boundary Scan (JTAG) support.  
SXT6051  
System Block Diagram  
SETS  
POH  
Serial Accesses  
MMSP  
Bus  
SOH  
Serial Accesses  
SXT 6051  
Transm it  
Master  
Clock In  
OHT  
TX  
4
TBus Tim ing  
AU-3/4 &  
VC-3/4  
Transm it Processor  
STM -0 / STM -1  
Transm it Section  
Term ination &  
Protection Function  
(RST, M ST, M SP)  
Transm it  
Tx Clock out  
Telecom  
Bus Add  
Interface  
6.48M/19.44M Clock  
Telecom Bus Data  
Data  
(HPT, M SA(PP))  
1
8
or 8 (S TM -0)  
(STM -1)  
SXT 6251  
21 Channel  
Mapper  
STM -0/1  
Line  
Interface  
Microcontroller Interface (Intel/Motorola selectable)  
1
8
or  
8 (S TM -0)  
(STM -1)  
Data  
Clock  
LOS  
Receive  
Telecom  
Bus  
Drop  
Interface  
AU-3/4 &  
VC-3/4  
Receive Processor  
STM -0 / STM -1  
Receive Section  
Term ination &  
Telecom Bus Data  
6.48M/19.44M Clock  
Protection Function  
(RST, M ST, M SP)  
TBus Tim ing  
(M SA,HPT&Retim ing)  
4
RX  
optional retim ing  
Clock&tim ing  
POH  
Serial Accesses  
DMSP  
Bus  
SOH  
Serial Accesses  
1234567...144

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