Datasheet > STVA16857AGLF

STVA16857AGLF

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管电视
页数	文件大小	规格书
13页	126K
描述
D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, 6.10 MM WIDTH, 0.50 MM PITCH, MO-153, LEAD FREE, TSSOP-48

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STVA16857AGLF 数据手册

ICSSSTVA16857

Integrated

Circuit

Systems, Inc.

DDR 14-Bit Registered Buffer

Recommended Applications:

Pin Configuration

•

DDR Memory Modules

GND

VDDQ

GND

VDDQ

GND

VDD

CLK#

CLK

VDD

GND

VREF

RESET#

•

Provides complete DDR DIMM logic solution with

ICS93V857 or ICS95V857

•

SSTL_2 compatible data registers

DDR400 recommended (backward compatible to

DDR200/266/333)

Product Features:

•

Exceeds "SSTVN16857" performance

VDDQ

GND

•

Differential clock signal

•

Meets SSTL_2 signal data

Supports SSTL_2 class I & II specifications

Low-voltage operation

- V_DD= 2.3V to 2.7V

48 pin TSSOP package

VDDQ

GND

Q10

Q11

Q12

VDDQ

GND

Q13

Q14

D10

D11

D12

VDD

GND

D13

D14

•

Truth Table¹

Inputs

CLK CLK#

X or X or

Q Outputs

48-Pin TSSOP

6.10 mm. Body, 0.50 mm. pitch = TSSOP

RESET#

X or

Floating Floating Floating

↑

↓

Q₀⁽²⁾

L or H

Notes:

H = High Signal Level

L = Low Signal Level

↑ = Transition LOW-to-HIGH

↓ = Transition HIGH -to LOW

X = Irrelevant

Block Diagram

CLK

CLK#

Output level before the indicated

steady state input conditions were

established.

RESET#

CLK

VREF

To 13 Other Channels

0932A—05/12/04

12 3 4 5 6 7...13

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