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STV8162D PDF预览

STV8162D

更新时间: 2024-02-03 23:07:13
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 线性稳压器IC调节器电源电路光电二极管输出元件
页数 文件大小 规格书
12页 172K
描述
+5 V, +5 V and +8 V Triple-Voltage Regulator with Disable and Reset Functions

STV8162D 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:PLASTIC, DIP-18
针数:18Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
可调性:FIXED标称回动电压 1:1 V
最大绝对输入电压:20 V最大输入电压:18 V
最小输入电压:7 VJESD-30 代码:R-PDIP-T18
JESD-609代码:e3长度:22.86 mm
最大电网调整率:0.08%最大负载调整率:0.16%
功能数量:1输出次数:3
端子数量:18工作温度TJ-Max:140 °C
工作温度TJ-Min:最大输出电流 1:0.6 A
最大输出电流 2:0.6 A最大输出电压 1:5.2 V
最小输出电压 1:4.8 V标称输出电压 1:5 V
最大输出电压 2:5.2 V最小输出电压 2:4.8 V
标称输出电压 2:5 V封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP18,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
调节器类型:FIXED POSITIVE MULTIPLE OUTPUT STANDARD REGULATOR座面最大高度:5.33 mm
子类别:Other Regulators表面贴装:NO
技术:BIPOLAR端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
最大电压容差:4%宽度:7.62 mm
Base Number Matches:1

STV8162D 数据手册

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®
STV8162 - STV8162D  
+5 V, +5 V and +8 V Triple-Voltage Regulator  
with Disable and Reset Functions  
DATASHEET  
Key Features  
Input Voltage range between 7 V and 18 V  
Output Currents up to 600 mA  
Fixed Precision Output 1 voltage of 5 V ± 2%  
Fixed Precision Output 2 voltage of 5 V ± 2%  
Fixed Precision Output 3 voltage of 8 V ± 2%  
Output 1 with Reset facility  
Clipwatt 11  
Order Code: STV8162  
Outputs 2 and 3 can be disabled by digital input  
Short Circuit Protection on each output  
Thermal Protection  
Low Dropout Voltages  
DESCRIPTION  
The STV8162 and STV8162D are monolithic triple  
positive voltage regulators designed to provide three  
fixed precision output voltages of 5 V, 5 V and 8 V for  
currents up to 0.6 A.  
Power DIP 18 (9 + 9)  
Order Code: STV8162D  
An internal reset circuit generates a reset pulse  
when the voltage of Output 1 drops below the  
regulated voltage value.  
Outputs 2 and 3 can be disabled by a digital input.  
Short-circuit and thermal protections are included in  
all versions.  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
9
8
7
6
5
4
3
2
1
10  
11  
12  
13  
14  
15  
16  
17  
18  
DISABLE  
INPUT3  
11  
10  
9
8
7
6
5
4
3
NC  
DISABLE  
INPUT3  
OUTPUT3  
INPUT2  
GROUND  
OUTPUT2  
INPUT1  
Top View  
OUTPUT3  
INPUT2  
OUTPUT2  
INPUT1  
OUTPUT1  
DELAY CAPACITOR  
RESET  
OUTPUT1  
DELAY CAPACITOR  
RESET  
2
1
February 2004  
1/12  

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