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STV7622/BMP PDF预览

STV7622/BMP

更新时间: 2024-09-23 13:14:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 驱动器
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32页 314K
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STV7622/BMP 数据手册

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STV7622  
192 output plasma display panel data driver  
Preliminary Data  
The input data bus is configured by dedicated  
input pins:  
Features  
192 high-voltage outputs  
BS1 and BS2: bus width select (3, 6,  
Output pad placements: I-shape  
90V absolute maximum supply  
2 × 3 bits or RSDS mode)  
DIR input: shift register loading direction  
EMI control features:  
– SmartSlope  
The STV7622 output stage integrates several ST  
patented functions aimed at reducing EMI without  
compromising addressing speed or performance  
of the PDP modules.  
– ConstantSlope  
– Spread Spectrum Jitter (SSJ)  
These functions mainly consist of:  
Configurable data bus:  
SmartSlope: controls the output falling edge  
speed /shape  
– 3, 6 or 2 × 3 bits  
– TTL and LVCMOS compatible  
– RSDS mode  
ConstantSlope: controls the output rising  
edge speed  
– Single- or dual-edge clocking mode  
– 60MHz clock frequency  
Spread Spectrum Jitter (SSJ): controls the  
spread of the output rising edge  
3.3/5V CMOS logic compatible  
The STV7622 is powered by a separate 70V  
supply for the high-voltage outputs and a 5V  
supply for the logic. All command input levels are  
5V CMOS as well as 3.3V compatible.  
- 60/+24mA source/sink output current  
capability  
BCD Process  
Packaging according to customer request:  
wafer, die, bumped die/wafer, TCP or COF  
Figure 1.  
Block diagram  
BS1 BS2  
DIR  
CLK1  
CLK2  
VDD  
VSSLOG  
Description  
32-bit Shift register  
32-bit Shift register  
32-bit Shift register  
32-bit Shift register  
32-bit Shift register  
32-bit Shift register  
DB1  
DB2  
DB3  
DB4  
DB5  
DB6  
The STV7622 is a data driver for Plasma Display  
Panels (PDP) designed in the ST’s proprietary  
BCD high-voltage technology.  
TEST1  
TEST2  
It controls up to 192 outputs via an input data bus  
(3, 6 or 2 × 3-bits wide) operating at up to 60MHz.  
This large number of outputs reduces the number  
of connections between the controller board and  
the data driver ICs.  
VREF  
10nF  
Data decoding  
Q1 Q2 Q3 Q4  
Q192  
/STB1  
/STB2  
Latch  
VCC  
RS1  
RS2  
FS1  
FS2  
/BLK  
POC  
Output control / EMI control  
Output buffer stage  
The STV7622 contains a new logic input stage  
that minimizes EMI resulting from the  
transmission of high speed TTL or LVCMOS data  
and clock signals. This new input stage is RSDS  
compliant. It enables increasing the operating  
frequency without compromising noise immunity.  
VPP  
VSSP  
VSSSUB  
OUT1 OUT2 OUT3 …..  
…. OUT192  
May 2007  
Rev 1  
1/32  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to  
change without notice.  
www.st.com  
32  

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