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STSR2CD PDF预览

STSR2CD

更新时间: 2024-11-26 22:42:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 驱动
页数 文件大小 规格书
12页 290K
描述
FORWARD SYNCHRONOUS RECTIFIERS SMART DRIVER

STSR2CD 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
高边驱动器:YES接口集成电路类型:BUFFER OR INVERTER BASED MOSFET DRIVER
JESD-30 代码:R-PDSO-G8JESD-609代码:e4
长度:4.9 mm湿度敏感等级:1
功能数量:1端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
标称输出峰值电流:3.5 A封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:MOSFET Drivers最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm

STSR2CD 数据手册

 浏览型号STSR2CD的Datasheet PDF文件第2页浏览型号STSR2CD的Datasheet PDF文件第3页浏览型号STSR2CD的Datasheet PDF文件第4页浏览型号STSR2CD的Datasheet PDF文件第5页浏览型号STSR2CD的Datasheet PDF文件第6页浏览型号STSR2CD的Datasheet PDF文件第7页 
STSR2  
FORWARD SYNCHRONOUS  
RECTIFIERS SMART DRIVER  
SUPPLY VOLTAGE RANGE: 4.5V TO 5.5V  
TYPICAL PEAK OUTPUT CURRENT:  
SOURCE -2A, SINK 3.5A  
OPERATING FREQUENCY: 20 TO 750 KHZ  
SMART TURN-OFF ANTICIPATION TIMING  
OPERATION INDEPENDENT FROM THE  
FORWARD MAGNETIC RESET TECHNIQUE  
POSSIBILITY TO OPERATE IN  
DISCONTINUOUS MODE  
SO-8  
DESCRIPTION  
while the anticipation in turning off the OUT  
GATE2  
can be set through external components. The  
adopted transitions revelation mechanism makes  
circuit operation independent by the forward  
magnetic reset technique used, avoiding most of  
the common problems inherent in self-driven  
synchronous rectifiers. A special Inhibit function  
STSR2 Smart Driver IC provides two  
complementary high current outputs to drive  
Power Mosfets. The IC is dedicated to properly  
drive secondary Synchronous Rectifiers in  
medium power, low output voltage, high efficiency  
Forward Converters. From a synchronizing clock  
input, STSR2 generates two driving signals with  
the self-setting of dead time between  
complementary pulses. The IC operation prevents  
allows the shut-off of OUT  
. This feature  
GATE2  
makes discontinuous conduction mode possible  
and prevents the freewheeling mosfet from  
sinking current from the output.  
secondary  
side  
shoot-through  
conditions  
STSR2 automatically turns off the outputs when  
duty-cycle is lower than 13%, while STSR2M  
works even at very low duty-cycle values.  
providing proper timing at the outputs turn-off  
transition. This smart function operates through a  
fast cycle-after-cycle control logic mechanism  
based on an internal high frequency oscillator,  
synchronized by the clock signal.  
A
fixed  
with  
anticipation in turning-off the OUT  
GATE1  
respect to the clock signal transition is provided,  
SCHEMATIC DIAGRAM  
Vcc  
2
5.7V  
+
BIAS  
UVLO  
PEAK  
DETECTOR  
ANTICIPATION  
SET  
SETANT2  
3
4
CK  
+
+
HIGH  
FREQUENCY  
OSCILLATOR  
1
7
OUTGate1  
OUTGate2  
OUTPUT  
BUFFERS  
DIGITAL  
CONTROL  
-
+
INHIBIT  
5
25mV  
6
8
SGLGND  
PWRGND  
June 2003  
1/12  

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