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STSMIA832TBR PDF预览

STSMIA832TBR

更新时间: 2024-11-27 03:30:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 线路驱动器或接收器解码器驱动程序和接口接口集成电路
页数 文件大小 规格书
23页 434K
描述
1.8V/2.8V High speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer

STSMIA832TBR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:TFBGA, BGA25,5X5,20针数:25
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.71
Is Samacsys:N差分输出:NO
输入特性:DIFFERENTIAL接口集成电路类型:LINE RECEIVER
接口标准:GENERAL PURPOSEJESD-30 代码:S-PBGA-B25
JESD-609代码:e1长度:3 mm
功能数量:1端子数量:25
最高工作温度:85 °C最低工作温度:-40 °C
最大输出低电流:0.004 A封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA25,5X5,20
封装形状:SQUARE封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.8 V
认证状态:Not Qualified最大接收延迟:8.5 ns
接收器位数:1座面最大高度:1.16 mm
子类别:Line Driver or Receivers最大压摆率:9 mA
最大供电电压:3.6 V最小供电电压:2.65 V
标称供电电压:2.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
Base Number Matches:1

STSMIA832TBR 数据手册

 浏览型号STSMIA832TBR的Datasheet PDF文件第2页浏览型号STSMIA832TBR的Datasheet PDF文件第3页浏览型号STSMIA832TBR的Datasheet PDF文件第4页浏览型号STSMIA832TBR的Datasheet PDF文件第5页浏览型号STSMIA832TBR的Datasheet PDF文件第6页浏览型号STSMIA832TBR的Datasheet PDF文件第7页 
STSMIA832  
1.8V/2.8V High speed dual differential line receivers,  
standard mobile imaging architecture (SMIA) decoder deserializer  
Feature summary  
Sub-low voltage differential signaling inputs:  
V
ID = 100mV MIN. with RT = 100, CL = 10pF  
High signaling rate:  
IN = 650 Mbps MAX (D+,D-,STRB+,STRB-)  
fOUT = 82 MHz MAX (CLK)  
OUT = 82 Mbps MAX (for each data line D1-D8)  
f
µTFBGA25  
f
Very high speed strobe to clock:  
Description  
tpLH~tpHL=5.2ns (TYP) at VDD=2.8V; VL=1.8V  
The STSMIA832 receiver converts the subLVDS  
clock/datastream (up to 650 Mbps throughput  
bandwidth) back into parallel 8 bits of  
Operating voltage range:  
VDD(OPR) = 2.65V to 3.6V  
VL(OPR) =1.65V to 1.95V  
CMOS/LVTTL. The device recognizes the SMIA  
32 bit start of frame (SOF), end of frame (EOF),  
start of line (SOL) and end of line (EOL)  
sequences to generate the H-SYNC and V-SYNC  
signals. Output LVTTL clock (up to 82 MHz) is  
transmitted in parallel with data. Output data are  
rising-edge strobes. This chipset is an ideal  
means to link mobile camera modules to  
Symmetrical output impedance (D1-D8, H-  
SYNC, V-SYNC, CLK):  
IIOHI=IOL=4mA (MIN) at VDD=2.65V;VL=1.8V  
Low power dissipation (DISABLED: EN=Gnd):  
ISOFF = IDD + IL = 10 µA (Max)  
SMIA specification compliant  
CLASS 0 and CLASS 1,2 supported (config by  
Baseband processors. In order to minimize static  
current consumption, it is possible to shut down  
the device when the interface is not being used by  
a power-down (EN) pin that reduces the  
Maximum Current Consumption to 10 µA making  
this device ideal for portable applications like  
Mobile Phone and Portable Battery Equipment. A  
configurable input (Class_Sel) is provided to  
select different CLASS (0 or 1,2) mode inside the  
SMIA STD specifications.  
CLASS_SEL)  
CMOS logic input threshold  
(EN, SYNC_SEL, CLASS_SEL):  
VIL = 0.3xVL; VL = 1.65V to 1.95V  
VIH = 0.7xVL; VL = 1.65V to 1.95V  
3.6V tolerant on inputs  
(EN, SYNC_SEL, CLASS_SEL)  
32 BIT synchronization codes (SOF, EOF,  
SOL, EOL)  
The STSMIA832 is offered in a µTFBGA package  
to optimize PCB space. All inputs and outputs are  
equipped with protection circuits against static  
discharge, giving them ESD immunity from  
transient excess voltage. The STSMIA832 is  
characterized for operation over the commercial  
temperature range -40°C to 85°C.  
Leadfree µTFBGA package  
(RoHS Restriction of hazardous substances)  
Order codes  
Temperature  
Part number  
Package  
Packaging  
Range  
STSMIA832TBR  
May 2006  
-40 to 85 °C  
µTFBGA25 3x3mm (TAPE & REEL)  
Rev. 2  
3000 parts per reel  
1/23  
www.st.com  
23  

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