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STSMIA832

更新时间： 2024-11-27 03:30:47

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		解码器
页数	文件大小	规格书
23页	434K
描述
1.8V/2.8V High speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer

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STSMIA832 数据手册

STSMIA832

1.8V/2.8V High speed dual differential line receivers,

standard mobile imaging architecture (SMIA) decoder deserializer

Feature summary

■ Sub-low voltage differential signaling inputs:

_ID= 100mV MIN. with R_T= 100Ω, C_L= 10pF

■ High signaling rate:

_IN= 650 Mbps MAX (D+,D-,STRB+,STRB-)

f_OUT= 82 MHz MAX (CLK)

_OUT= 82 Mbps MAX (for each data line D1-D8)

µTFBGA25

■ Very high speed strobe to clock:

Description

tp_LH~tp_HL=5.2ns (TYP) at V_DD=2.8V; V_L=1.8V

The STSMIA832 receiver converts the subLVDS

clock/datastream (up to 650 Mbps throughput

bandwidth) back into parallel 8 bits of

■ Operating voltage range:

V_DD(OPR) = 2.65V to 3.6V

V_L(OPR) =1.65V to 1.95V

CMOS/LVTTL. The device recognizes the SMIA

32 bit start of frame (SOF), end of frame (EOF),

start of line (SOL) and end of line (EOL)

sequences to generate the H-SYNC and V-SYNC

signals. Output LVTTL clock (up to 82 MHz) is

transmitted in parallel with data. Output data are

rising-edge strobes. This chipset is an ideal

means to link mobile camera modules to

■ Symmetrical output impedance (D1-D8, H-

SYNC, V-SYNC, CLK):

II_OHI=I_OL=4mA (MIN) at V_DD=2.65V;V_L=1.8V

■ Low power dissipation (DISABLED: EN=Gnd):

I_SOFF= I_DD+ I_L= 10 µA (Max)

■ SMIA specification compliant

■ CLASS 0 and CLASS 1,2 supported (config by

Baseband processors. In order to minimize static

current consumption, it is possible to shut down

the device when the interface is not being used by

a power-down (EN) pin that reduces the

Maximum Current Consumption to 10 µA making

this device ideal for portable applications like

Mobile Phone and Portable Battery Equipment. A

configurable input (Class_Sel) is provided to

select different CLASS (0 or 1,2) mode inside the

SMIA STD specifications.

CLASS_SEL)

■ CMOS logic input threshold

(EN, SYNC_SEL, CLASS_SEL):

V_IL= 0.3xV_L; V_L= 1.65V to 1.95V

V_IH= 0.7xVL; V_L= 1.65V to 1.95V

■ 3.6V tolerant on inputs

(EN, SYNC_SEL, CLASS_SEL)

■ 32 BIT synchronization codes (SOF, EOF,

SOL, EOL)

The STSMIA832 is offered in a µTFBGA package

to optimize PCB space. All inputs and outputs are

equipped with protection circuits against static

discharge, giving them ESD immunity from

transient excess voltage. The STSMIA832 is

characterized for operation over the commercial

temperature range -40°C to 85°C.

■ Leadfree µTFBGA package

(RoHS Restriction of hazardous substances)

Order codes

Temperature

Part number

Package

Packaging

Range

STSMIA832TBR

May 2006

-40 to 85 °C

µTFBGA25 3x3mm (TAPE & REEL)

Rev. 2

3000 parts per reel

1/23

www.st.com

12 3 4 5 6 7...23

中文翻译

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与STSMIA832相关器件

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